参数资料
型号: AD872AJD
厂商: ANALOG DEVICES INC
元件分类: ADC
英文描述: Complete 12-Bit 10 MSPS Monolithic A/D Converter
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28
封装: SIDE BRAZED, CERAMIC, DIP-28
文件页数: 9/20页
文件大小: 330K
代理商: AD872AJD
REV. A
–9–
AD872A
T HE ORY OF OPE RAT ION
T he AD872A is implemented using a 4-stage pipelined multiple
flash architecture. A differential input track-and-hold amplifier
(T HA) acquires the input and converts the input voltage into a
differential current. A 4-bit approximation of the input is made
by the first flash converter, and an accurate analog representa-
tion of this 4-bit guess is generated by a digital-to-analog con-
verter. T his approximation is subtracted from the T HA output
to produce a remainder, or residue. T his residue is then sam-
pled and held by the second T HA, and a 4-bit approximation is
generated and subtracted by the second stage. Once the second
T HA goes into hold, the first stage goes back into track to
acquire a new input signal. T he third stage provides a 3-bit ap-
proximation/subtraction operation, and produces the final resi-
due, which is passed to a final 4-bit flash converter. T he 15
output bits from the 4 flash converters are accumulated in the
correction logic block, which adds the bits together using the
appropriate correction algorithm, to produce the 12-bit output
word. T he digital output, together with overrange indicator, is
latched into an output buffer to drive the output pins.
T he additional T HA inserted in each stage of the AD872A
architecture allows pipelining of the conversion. In essence, the
converter is converting multiple inputs simultaneously, process-
ing them through the converter chain serially. T his means that
while the converter is capable of capturing a new input sample
every clock cycle, it actually takes three clock cycles for the con-
version to be fully processed and appear at the output. T his
“pipeline delay” is often referred to as latency, and is not a con-
cern in most applications, however there are some cases where it
may be a consideration. For example, some applications call for
the A/D converter to be placed in a high speed feedback loop,
where its input is servoed to provide a desired result at the digi-
tal output (e.g., offset calibration or zero restoration in video
applications). In these cases the three clock cycle delay through
the pipeline must be accounted for in the loop stability calcula-
tions. Also, because the converter is working on three conver-
sions simultaneously, major disruptions to the part (such as a
large glitch on the supplies or reference) may corrupt three data
samples. Finally, there will be a minimum clock rate below
which the T HA droop corrupts the signal in the pipeline. In the
case of the AD872A, this minimum clock rate is 10 kHz.
T he high impedance differential inputs of the AD872A allow a
variety of input configurations (see APPLYING T HE AD872A),
T he AD872A converts the voltage difference between the V
INA
and V
INB
pins. For single-ended applications, one input pin
(V
INA
or V
INB
) may be grounded, but even in this case the differ-
ential input can provide a performance boost: for example, for
an input coming from a coaxial cable, V
INB
can be tied to the
shield ground, allowing the AD872A to reject shield noise as
common mode. T he high input impedance of the device mini-
mizes external driving requirements and allows the user to exter-
nally select the appropriate termination impedance for the
application.
T he AD872A clock circuitry uses both edges of the clock in its
internal timing circuitry (see spec page for exact timing require-
ments). T he AD872A samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock) the input T HA is in
track mode; during the clock high time it is in hold. System dis-
turbances just prior to the rising edge of the clock may cause the
part to acquire the wrong value, and should be minimized.
While the part uses both clock edges for its timing, jitter is only
a significant issue for the rising edge of the clock (see CLOCK
INPUT section).
APPLY ING T HE AD872A ANALOG INPUT S
T he AD872A features a high impedance differential input that
can readily operate on either single-ended or differential input
signals. T able I summarizes the nominal input voltage span for
both single-ended and differential modes, assuming a 2.5 V
reference input.
T able I. Input Voltage Span
V
INA
V
INB
V
INA
–V
INB
Single-Ended
+1 V
–1 V
+0.5 V
–0.5 V
GND
GND
–0.5 V
+0.5 V
+1 V (Positive Full Scale)
–1 V (Negative Full Scale)
+1 V (Positive Full Scale)
–1 V (Negative Full Scale)
Differential
Figure 10 shows an approximate model for the analog input cir-
cuit. As this model indicates, when the input exceeds 1.6 V
(with respect to AGND), the input device may saturate, causing
the input impedance to drop substantially and significantly re-
ducing the performance of the part. Input compliance in the
negative direction is somewhat larger, showing virtually no deg-
radation in performance for inputs as low as –1.9 V.
+5V
1.75mA
+1.6V
5pF
–1.9V
–5V
1.75mA
V
INA
OR V
INB
6
1V
AD872A
Figure 10. AD872A Equivalent Analog Input Circuit
Figure 11 illustrates the effect of varying the common-mode
voltage of a –0.5 dB input signal on total harmonic distortion.
–1 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
CM INPUT VOLTAGE – V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
Figure 11. AD872A Total Harmonic Distortion vs. CM Input
Voltage, f
IN
= 1 MHz, FS = 10 MSPS
相关PDF资料
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AD872AJE Complete 12-Bit 10 MSPS Monolithic A/D Converter
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