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参数资料
| 型号： | AD9054PCB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit, 200 MSPS A/D Converter |
| 中文描述： | 8位，200 MSPS的A / D转换 |
| 文件页数： | 13/20页 |
| 文件大小： | 303K |
| 代理商： | AD9054PCB |
AD9054
–13–
REV. 0
the specification table. In this case the DS hold time specifica-
tion on the rising edge can be ignored.
Applications that will continuously update the synchronization
command need to treat the DS signal as a pulse and satisfy
timing requirements on both rising and falling edges. It is easiest
to consider the DS signal in this case to be a pulse train at one
half the encode rate, the positive pulse nominally bracketing the
ENCODE falling edge on alternate cycles as shown in the tim-
ing diagram (Figure 2). T he falling/rising edge of DS has to
satisfy a minimum setup time (T
SDS
) before the rising/falling
edge of ENCODE; similarly, the rising/falling edge of DS has to
satisfy a minimum hold time (T
HDS
) relative to the rising/falling
edge of ENCODE. DS can fall a minimum of T
HDS
after
ENCODE falls and a maximum of T
SDS
before the next
ENCODE rises. DS can rise a minimum of T
HDS
after
ENCODE rises and a maximum of T
SDS
before ENCODE
falls. T his timing requirement produces a tight timing window
at higher encode rates. Synchronization by a single reset edge
results in a simpler timing solution in many applications. For
example, synchronization may be provided at the beginning of
each graphics line or frame.
T he data are presented at the output of the AD9054 in a ping-
pong (alternating) fashion to optimize the performance of the
converter. It may be aligned for presentation as sixteen bits in
parallel by adding a register stage to the output.
In Dual Channel Mode, the converted data is produced five
clock cycles after the rising edge of ENCODE on which the
sample is taken (five pipeline delays).
VIN
0.1
m
F
1k
V
0.1
m
F
0.1
m
F
NC
CLOCK
VREF OUT
VREF IN
AIN
AIN
DEMUX
AD9054
DS
DS
ENC
ENC
A PORT
DS
'573
B PORT
'74
DIVIDE
BY 2
NC = NO CONNECT
Figure 36. Dual Port Mode—Aligned Output Data
In Figure 36, the converter is operating in Dual Port Mode,
with data coming alternately out of Port A and Port B. T he
figure illustrates how the output data may be aligned with an
output latch to produce a 16-bit output at 1/2 the conversion
clock rate. T he Data Sync input must be properly exercised to
time the A Port with the synchronizing latch.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9057 | 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057BRS-80 | 8-Bit 40 MSPS/50 MSPS/80 MSPS Converter |
| AD9057BRS-40 | 8-Bit 40 MSPS/50 MSPS/80 MSPS Converter |
| AD9057BRS-60 | 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057PCB | 8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9057 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057/PCB | 制造商:Analog Devices 功能描述:EVAL KIT FOR ADC, 8BIT 40MSPS/60MSPS/80MSPS A/D CNVRTR - Bulk |
| AD9057_03 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057-40 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
| AD9057-60 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit 40 MSPS/60 MSPS/80 MSPS A/D Converter |
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