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参数资料
| 型号： | AD9100* |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Ultrahigh Speed Monolithic Track-and-Hold |
| 中文描述： | 超高速单片跟踪和保持 |
| 文件页数： | 4/12页 |
| 文件大小： | 440K |
AD9100
REV. B
–4–
PIN FUNCTION DESCRIPTIONS/CONNECTIONS
Pin No.
Description
Connection
1
2, 3, 8, 10–13, 17
4
5, 7
6, 15
9
14, 16, 20
18
19
–V
S
GND
V
IN
–V
S
BYPASS
V
OUT
+V
S
CLK
CLK
–5.2 V Power Supply
Common Ground Plane
Analog Input Signal
–5.2 V Power Supply
0.1
μ
F to Ground
Track-and-Hold Output
+5 V, Power Supply
Complement ECL Clock
“True” ECL Clock
CHIP PAD ASSIGNMENTS
GND
NC
CLOCK
NC
(NOTE 3)
2
3
4
5
6
7
8
9
10
11
12
32
14
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
31
+V
S
CAP
(NOTE 1)
CLOCK
GND
NC
BYPASS
AD9100
(Not to scale)
+V
S
+V
S
+V
S
+V
S
+V
S
+V
S
BYPASS
(NOTE 2)
+V
S
+V
OUT
–V
S
–V
IN
–V
S
–V
S
CAP
(NOTE 1)
–V
S
3
63
3
15 mils
m
F CERAMIC
SIZE = 148
2. 0.01
m
F CERAMIC CONNECTED BETWEEN PAD 29 AND PAD 31.
3. HOLD CAPACITOR CONNECTED FROM PAD 4 AND PAD 5 TO
NC = NO CONNECT
1
13
27
BYPASS
–V
S
GND
+V
S
CLK
–V
S
–V
S
+V
S
BYPASS
+V
S
GND
V
IN
CLK
GND
GND
GND
V
OUT
GND
GND
GND
TOP VIEW
(Not to Scale)
AD9100
PIN CONFIGURATION
20-Lead Side-Brazed Ceramic DIP
TERMINOLOGY
Analog Delay
is the time required for an analog input signal to
propagate from the device input to output.
Aperture Delay
tells when the input signal is actually sampled.
It is the time difference between the analog propagation delay of
the front-end buffer and the control switch delay time. (The
time from the hold command transition to when the switch is
opened.) For the AD9100, this is a positive value which means
that the switch delay is longer than the analog delay.
Aperture Jitter
is the random variation in the aperture delay.
This is measured in ps-rms and results in phase noise on the
held signal.
Droop Rate
is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9100 output with the
device in hold mode and the input held at a specified dc value,
the measurement starts immediately after the T/H switches from
track to hold. Feedthrough Rejection is the ratio of the input
signal to the output signal when in hold mode. This is a mea-
sure of how well the switch isolates the input signal from feeding
through to the output.
Hold-to-Track Switch Delay
is the time delay from the track
command to the point when the output starts to change and
acquire a new signal.
Pedestal Offset
is the offset voltage step measured immediately
after the AD9100 is switched from track to hold with the input
held at zero volts. It manifests itself as an added offset during
the hold time.
Track-to-Hold Settling Time
is the time necessary for the
track to hold switching transient to settle to within 1 mV of its
final value.
Track-to-Hold Switching Transient
is the maximum peak
switch induced transient voltage which appears at the AD9100
output when it is switched from track to hold.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9100 | Ultrahigh Speed Monolithic Track-and-Hold(超高速单片跟踪保持放大器) |
| AD9101AE | 125 MSPS Monolithic Sampling Amplifier |
| AD9101AR | 125 MSPS Monolithic Sampling Amplifier |
| AD9101SE | 125 MSPS Monolithic Sampling Amplifier |
| AD9101 | 125 MSPS Monolithic Sampling Amplifier(125MSPS单片采样放大器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9100AD | 制造商:AD 制造商全称:Analog Devices 功能描述:Ultrahigh Speed Monolithic Track-and-Hold |
| ad9100ae | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9100JD | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| AD9100SD | 制造商:AD 制造商全称:Analog Devices 功能描述:Ultrahigh Speed Monolithic Track-and-Hold |
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