参数资料
型号: AD9201ARSZ
厂商: Analog Devices Inc
文件页数: 14/20页
文件大小: 0K
描述: IC ADC CMOS 10BIT DUAL 28-SSOP
标准包装: 47
位数: 10
采样率(每秒): 20M
数据接口: 并联
转换器数目: 2
功率耗散(最大): 245mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 管件
输入数目和类型: 4 个单端,单极;2 个差分,单极
产品目录页面: 780 (CN2011-ZH PDF)
–3–
REV. D
AD9201
Parameter
Symbol
Min
Typ
Max
Units
Condition
DYNAMIC PERFORMANCE (SE)3
Signal-to-Noise and Distortion
SINAD
f = 3.58 MHz
52.3
dB
Signal-to-Noise
SNR
f = 3.58 MHz
55.5
dB
Total Harmonic Distortion
THD
f = 3.58 MHz
–55
dB
Spurious Free Dynamic Range
SFDR
f = 3.58 MHz
–58
dB
DIGITAL INPUTS
High Input Voltage
VIH
2.4
V
Low Input Voltage
VIL
0.3
V
DC Leakage Current
IIN
±6
A
Input Capacitance
CIN
2pF
LOGIC OUTPUT (with DVDD = 3 V)
High Level Output Voltage
(IOH = 50
A)
VOH
2.88
V
Low Level Output Voltage
(IOL = 1.5 mA)
VOL
0.095
V
LOGIC OUTPUT (with DVDD = 5 V)
High Level Output Voltage
(IOH = 50
A)
VOH
4.5
V
Low Level Output Voltage
(IOL = 1.5 mA)
VOL
0.4
V
Data Valid Delay
tOD
11
ns
MUX Select Delay
tMD
7ns
Data Enable Delay
tED
13
ns
CL = 20 pF. Output Level to
90% of Final Value
Data High-Z Delay
tDHZ
13
ns
CLOCKING
Clock Pulsewidth High
tCH
22.5
ns
Clock Pulsewidth Low
tCL
22.5
ns
Pipeline Latency
3.0
Cycles
NOTES
1AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.
2IMD referred to larger of two input signals.
3SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.
Specifications subject to change without notice.
CLOCK
INPUT
SELECT
INPUT
DATA
OUTPUT
ADC SAMPLE
#1
ADC SAMPLE
#2
ADC SAMPLE
#3
ADC SAMPLE
#4
ADC SAMPLE
#5
Q CHANNEL
OUTPUT ENABLED
I CHANNEL
OUTPUT ENABLED
SAMPLE #1-3
Q CHANNEL
OUTPUT
SAMPLE #1-2
Q CHANNEL
OUTPUT
SAMPLE #1-1
Q CHANNEL
OUTPUT
SAMPLE #1-1
I CHANNEL
OUTPUT
SAMPLE #1
Q CHANNEL
OUTPUT
SAMPLE #1
I CHANNEL
OUTPUT
SAMPLE #2
Q CHANNEL
OUTPUT
tMD
tOD
Figure 1. ADC Timing
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