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| 型号： | AD9215BRU-80EB |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 圆形连接器 |
| 英文描述： | Circular Connector; No. of Contacts:18; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 |
| 中文描述： | 10位，65/80/105 MSPS的，3V的A / D转换 |
| 文件页数： | 14/36页 |
| 文件大小： | 1416K |
| 代理商： | AD9215BRU-80EB |
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AD9215
APPLYING THE AD9215 THEORY OF OPERATION
The AD9215 architecture consists of a front-end SHA followed
by a pipelined switched capacitor ADC. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 10-bit result in the digital correction logic. The pipe-
lined architecture permits the first stage to operate on a new
input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Rev. A | Page 14 of 36
The input stage contains a differential SHA that can be config-
ured as ac-coupled or dc-coupled in differential or single-ended
modes. Each stage of the pipeline, excluding the last, consists of
a low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipe-
line. Redundancy is used in each one of the stages to facilitate
digital correction of flash errors.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjust-
ment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
Analog Input and Reference Overview
The analog input to the AD9215 is a differential switched
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA input
can support a wide common-mode range and maintain excel-
lent performance, as shown in Figure 31. An input common-
mode voltage of midsupply minimizes signal-dependent errors
and provides optimum performance.
0
H
H
VIN+
VIN–
C
PAR
C
PAR
T
T
0.5pF
0.5pF
T
T
Figure 30. Switched-Capacitor SHA Input
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 30). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s in-
put; therefore, the precise values are dependent upon the appli-
cation. In IF undersampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they would limit the input bandwidth.
The analog inputs of the AD9215 are not internally dc biased.
In ac-coupled applications, the user must provide this bias ex-
ternally.
V
CM
=
AVDD
/2 is recommended for optimum per-
formance, but the device functions over a wider range with rea-
sonable performance (see Figure 31).
0
40
0.25
45
50
55
60
65
70
75
80
85
0.75
1.25
1.75
2.25
2.75
d
ANALOG INPUT COMMON-MODE VOLTAGE (V)
2V p-p SFDR
2V p-p SNR
Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as
REFT
= 1/2
(
AVDD
+
VREF
)
REFB
= 1/2 (
AVDD
VREF
)
Span
=
2
×
(
REFT
REFB
)
=
2 ×
VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed val-
ues of 0.5 V or 1.0 V or adjusted within the same range as dis-
cussed in the Internal Reference Connection section. Maximum
相关PDF资料 |
PDF描述 |
|---|---|
| AD9216BCPZRL7-65 | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| AD9216 | Static Monitor |
| AD9216-105 | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| AD9216-105PCB | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| AD9216-40PCB | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9215BRURL7-105 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215BRURL7-65 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9215BRURL7-80 | 制造商:Analog Devices 功能描述: |
| AD9215BRUZ-105 | 功能描述:IC ADC 10BIT 105MSPS 3V 28-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| AD9215BRUZ-105 | 制造商:Analog Devices 功能描述:AD CONVERTOR ((NW)) |
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