- 您现在的位置：买卖IC网 > PDF目录10255 > AD9215BRUZ-65 (Analog Devices Inc)IC ADC 10BIT 65MSPS 3V 28TSSOP PDF资料下载
参数资料
| 型号： | AD9215BRUZ-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 65MSPS 3V 28TSSOP |
| 设计资源： | Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003) Interfacing the High Frequency AD8331 to AD9215 (CN0096) |
| 标准包装： | 50 |
| 位数： | 10 |
| 采样率（每秒）： | 65M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 96mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
| 配用： | AD9215BCP-80EBZ-ND - BOARD EVAL FOR AD9215BCP-80 AD9215BCP-65EBZ-ND - BOARD EVAL FOR AD9215BCP-65 AD9215BCP-105EBZ-ND - BOARD EVAL FOR AD9215BCP-105 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页
AD9215
Data Sheet
Rev. B | Page 8 of 36
EQUIVALENT CIRCUITS
02874-A-005
AVDD
MODE
Figure 5. Equivalent Analog Input Circuit
02874-A-006
AVDD
MODE
20k
Figure 6. Equivalent MODE Input Circuit
02874-A-007
D9–D0,
OR
DRVDD
Figure 7. Equivalent Digital Output Circuit
02874-A-008
2.6k
2.6k
AVDD
CLK
Figure 8. Equivalent Digital Input Circuit
DEFINITIONS OF SPECIFICATIONS
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as frequency-dependent noise
on the input to the ADC.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated perfor-
mance. Pulse width low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these speci-
fications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicate that all 1024
codes, respectively, must be present over all operating ranges.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula, it is possible to obtain a
measure of performance expressed as N, the effective number of
bits
N = (SINAD – 1.76)/6.02
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur at
an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between the first
and last code transitions and the ideal difference between the
first and last code transitions.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN. Zero error is defined as the deviation
of the actual transition from that point.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Output Propagation Delay
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
相关PDF资料 |
PDF描述 |
|---|---|
| VI-23T-CU-F4 | CONVERTER MOD DC/DC 6.5V 200W |
| AD7858LARSZ-REEL | IC ADC 12BIT 8CHAN SRL 24SSOP |
| VI-23T-CU-F2 | CONVERTER MOD DC/DC 6.5V 200W |
| VE-22P-MX-F4 | CONVERTER MOD DC/DC 13.8V 75W |
| AD7858LARZ-REEL | IC ADC 12BIT 8CHAN SRL 24SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9215BRUZ-65 | 制造商:Analog Devices 功能描述:10BIT ADC 65MSPS 9215 TSSOP28 |
| AD9215BRUZ-80 | 功能描述:IC ADC 10BIT 80MSPS 3V 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD9215BRUZ-80 | 制造商:Analog Devices 功能描述:10BIT ADC 80MSPS 9215 TSSOP28 |
| AD9215BRUZRL7-105 | 功能描述:IC ADC 10BIT 105MSPS 3V 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| AD9215BRUZRL7-65 | 功能描述:IC ADC 10BIT 65MSPS 3V 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
发布紧急采购，3分钟左右您将得到回复。