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参数资料
| 型号： | AD9218-65PCB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| 中文描述： | 10位，40/65/80/105 MSPS的3伏双A / D转换 |
| 文件页数： | 8/24页 |
| 文件大小： | 1591K |
| 代理商： | AD9218-65PCB |
REV. 0
AD9218
–8–
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level (–40 dBFS)
signal when the adjacent interfering channel is driven by a
full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180
degrees out of phase. Peak-to-peak differential is computed by
rotating the inputs phase 180 degrees and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
ENOB
SNR
dB
MEASURED
=
–
.
1 76
.
6 02
ENCODE Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing t
ENCH
in text. At a given clock rate, these specifica-
tions define an acceptable ENCODE duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Power
V
Z
0 001
.
Full Scale
Full Scale rms
INPUT
=
10
2
log
Gain Error
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a
“
best straight line
”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Noise (for Any Range within the ADC)
V
Z
NOISE
FS
SNR
Signal
dBm
dBc
10
dBFS
=
×
0 001 10
.
Where
Z
is the input impedance,
FS
is the full scale of the
device for the frequency in question,
SNR
is the value for the
particular input level, and
Signal
is the signal level within the
ADC reported in dB below full scale. This value includes both
thermal and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
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| AD9218BST-105 | 功能描述:IC ADC 10BIT DUAL 105MSPS 48LQFP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9218BST-40 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 40Msps 10-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DUAL 10 BIT 105/80/65/40 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NW)) |
| AD9218BST-65 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 65Msps 10-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DUAL 10 BIT 105/80/65 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:IC 10-BIT ADC |
| AD9218BST-80 | 制造商:Analog Devices 功能描述:ADC Dual Pipelined 80Msps 10-bit Parallel 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 10-BIT ADC |
| AD9218BST-RL105 | 功能描述:IC ADC 10BIT DUAL 105MSPS 48LQFP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
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