参数资料
型号: AD9286-500EBZ
厂商: Analog Devices Inc
文件页数: 16/28页
文件大小: 0K
描述: BOARD EVAL FOR AD9286-500
标准包装: 1
ADC 的数量: 2
位数: 8
采样率(每秒): 500M
数据接口: 串行,SPI?
输入范围: 1.2 Vpp
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD9286
已供物品:
Data Sheet
AD9286
Rev. B | Page 23 of 28
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 13 are not currently supported for this device.
Table 13. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0
LSB first
Soft reset
1
Soft reset
LSB first
0
0x18
Nibbles are
mirrored so
that LSB-
first or MSB-
first mode
registers
correctly,
regardless of
shift mode
0x01
Chip ID
(global)
8-bit chip ID
0x0A
Unique chip
ID used to
differentiate
devices;
read only
0x02
Chip grade
(global)
Open
Speed grade ID
100 = 500 MSPS
Open
0x40
Unique
speed grade
ID used to
differentiate
devices;
read only
Device Index and Transfer Registers
0x05
Device
Index A
Open
ADC 2
default
ADC 1
default
0xFF
Bits are set to
determine
which on-
chip device
receives the
next write
command;
default is all
devices on
the chip
0xFF
Transfer
Open
Transfer
0xFF
Synchronous
transfer of
data from
the master
shift register
to the slave
Program Registers (May or may not be indexed by device index)
0x08
Modes
(global)
Open
Internal power-down mode
00: chip run
01: full power-down
10: reserved
11: reserved
0x00
Determines
various
generic
modes
of chip
operation
0x09
Clock
(global)
Open
Sample
mode
0: inter-
leaved
1: simul-
taneous
Open
Clock
boost
Duty cycle
stabilizer
0x09
0x0D
Test mode
(local)
Open
Reset
PN23 gen
Reset
PN9 gen
Open
Output test mode
000: off
001: midscale short
010: +FS short
011: FS short
100: checkerboard output
101: PN23 sequence
110: PN9 sequence
111: one-/zero-word toggle
0x00
When test
mode is set,
test data is
placed on
the output
pins in place
of normal
data
0x0E
BIST (local)
Open
BIST init
Open
BIST enable
0x00
BIST mode
config
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