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参数资料
| 型号： | AD9286-500EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9286-500 |
| 标准包装： | 1 |
| ADC 的数量： | 2 |
| 位数： | 8 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 输入范围： | 1.2 Vpp |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9286 |
| 已供物品： | 板 |
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AD9286
Data Sheet
Rev. B | Page 16 of 28
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9286 sample clock inputs,
CLK+ and CLK (and, optionally, AUXCLK+ and AUXCLK),
with a differential signal. The signal is typically ac-coupled into
the CLK+ and CLK pins via a transformer or capacitors.
Clock Input Options
The AD9286 has a very flexible clock input structure. The clock
input can be an LVDS, LVPECL, or sine wave signal. Each con-
figuration that is described in this section applies to both CLK+
and CLK and AUXCLK+ and AUXCLK, when necessary.
Figure 26 and Figure 27 show two preferred methods for clocking
the AD9286. A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun. The back-to-back Schottky diodes across the
transformer/balun secondary limit clock excursions into the
AD9286 to approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9286, while
preserving the fast rise and fall times of the signal that are
critical to low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2822
50 100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
CLOCK
INPUT
09338-
027
Figure 26. Transformer-Coupled Differential Clock
0.1F
SCHOTTKY
DIODES:
HSM2822
1nF
50
CLK–
CLK+
ADC
CLOCK
INPUT
09338-
028
Figure 27. Balun-Coupled Differential Clock
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
excellent jitter performance.
10
0
0.1F
240
50k
CLK–
CLK+
ADC
AD951x
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
09338-
029
Figure 28. Differential PECL Sample Clock
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 29. The AD9510/
clock drivers offer excellent jitter performance.
10
0
0.1F
50k
CLK–
CLK+
ADC
AD951x
LVDS DRIVER
CLOCK
INPUT
CLOCK
INPUT
09338-
030
Figure 29. Differential LVDS Sample Clock
Clocking Modes
The AD9286 powers up as a single-channel converter with inter-
leaving enabled. In this mode, a single high speed clock, driving
CLK+ and CLK, is divided down into two half-speed clocks
running 180° out of phase with each other, each driving their
respective ADC core. By strapping the two analog inputs together
externally, the AD9286 operates as a single 500 MSPS ADC.
Because the high sample rate is achieved by interleaving two
ADC cores, mismatch between the cores, board layout, and
clock timing can cause unwanted distortion. The AD9286 has
been designed with two well-matched ADC cores to minimize
mismatch. To aid the user in removing timing errors, the AD9286
provides both fine and coarse timing adjustments, per channel,
through SPI. These features are available at Register 0x37 (fine)
and Register 0x38 (coarse).
The AD9286 supports a mode that allows the user to provide
two separate half-speed clocks, bypassing the internal clock
timing circuits and permitting external control of the clock
timing relationship for each interleave channel. When the sample
mode is set to simultaneous (Address 0x09, Bit 3 = 1) and the
AUXCLKEN pin is tied to DRVDD, the AD9286 expects a second
clock on its auxiliary clock input (AUXCLK+, AUXCLK).
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| AD9287-100EB | 制造商:Analog Devices 功能描述: |
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