
AD9289
Rev. 0 | Page 4 of 32
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter
Temperature
Test Level
Min
Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
Full
IV
47.7
49.0
dB
fIN = 10.3 MHz
25°C
V
48.5
dB
fIN = 35 MHz
Full
VI
46.7
48.0
dB
SIGNAL-TO-NOISE RATIO (SINAD)
fIN = 2.4 MHz
Full
IV
47.6
48.9
dB
fIN = 10.3 MHz
25°C
V
48.4
dB
fIN = 35 MHz
Full
VI
46.2
47.5
dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
Full
IV
7.6
7.8
Bits
fIN = 10.3 MHz
25°C
V
7.7
Bits
fIN = 35 MHz
Full
VI
7.4
7.6
Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
Full
IV
61.0
70.0
dBc
fIN = 10.3 MHz
25°C
V
68.0
dBc
fIN = 35 MHz
Full
VI
54.0
65.0
dBc
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
Full
IV
–75.0
–61.0
dBc
fIN = 10.3 MHz
25°C
V
–70.0
dBc
fIN = 35 MHz
Full
VI
–65.0
–54.0
dBc
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
Full
IV
–70.0
–61.0
dBc
fIN = 10.3 MHz
25°C
V
–68.0
dBc
fIN = 35 MHz
Full
VI
–65.0
–57.5
dBc
TWO TONE INTERMOD DISTORTION (IMD)
AIN1 and AIN2 = –7.0 dBFS
fIN1 = 15 MHz
fIN2 = 16 MHz
25°C
V
–72.0
dBc
DIGITAL SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
Temperature
Test Level
Min
Typ
Max
Unit
Logic Compliance
LVDS
Differential Input Voltage
Full
IV
250
350
450
mV p-p
High Level Input Current
Full
VI
30
75
A
Low Level Input Current
Full
VI
30
75
A
Input Common-Mode Voltage
Full
IV
1.125
1.25
1.375
V
Input Resistance
25°C
V
100
k
Input Capacitance
25°C
V
2
pF
LOGIC INPUTS (DFS, PDWN, SHARED_REF)
Logic 1 Voltage
Full
IV
2.0
V
Logic 0 Voltage
Full
IV
0.8
V
Input Resistance
25°C
V
30
k
Input Capacitance
25°C
V
4
pF
LOGIC OUTPUTS (LOCK)
Logic 1 Voltage
Full
IV
2.45
V
Logic 0 Voltage
Full
IV
0.05
V
DIGITAL OUTPUTS (D1+, D1–)
Logic Compliance
LVDS
Differential Output Voltage
Full
VI
260
350
440
mV
Output Offset Voltage
Full
VI
1.15
1.25
1.35
V
Output Coding
Full
VI
Twos complement or binary
1 Clock inputs are LVDS-compatible. They require external dc bias and cannot be ac-coupled.