参数资料
型号: AD9430BSVZ-170
厂商: Analog Devices Inc
文件页数: 43/44页
文件大小: 0K
描述: IC ADC 12BIT 170MSPS 3.3V100TQFP
标准包装: 1
位数: 12
采样率(每秒): 170M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 1.43mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-TQFP 裸露焊盘
供应商设备封装: 100-TQFP-EP(14x14)
包装: 托盘
输入数目和类型: 1 个差分,单极
AD9430
Rev. E | Page 8 of 44
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
Test
AD9430-170
AD9430-210
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
Maximum Conversion Rate1
Full
VI
170
210
MSPS
Minimum Conversion Rate1
Full
V
40
MSPS
CLK+ Pulse Width High (tEH)1
Full
IV
2
12.5
2
12.5
ns
CLK+ Pulse Width Low (tEL)1
Full
IV
2
12.5
2
12.5
ns
DS Input Setup Time (tSDS)2
Full
IV
–0.5
ns
DS Input Hold Time (tHDS)2
Full
IV
1.75
ns
OUTPUT (CMOS Mode)
Valid Time (tV)
Full
IV
2
ns
Propagation Delay (tPD)
Full
IV
3.8
5
3.8
5
ns
Rise Time (tR) (20% to 80%)
25°C
V
1
ns
Fall Time (tF) (20% to 80%)
25°C
V
1
ns
DCO Propagation Delay (tCPD)
Full
IV
3.8
5
3.8
5
ns
Data to DCO Skew (tPD to tCPD)
Full
IV
–0.5
0
+0.5
–0.5
0
+0.5
ns
Interleaved Mode (A, B Latency)
Full
IV
14, 14
Cycles
Parallel Mode (A, B Latency)
Full
IV
15, 14
Cycles
OUTPUT (LVDS Mode)
Valid Time (tV)
Full
VI
2.0
ns
Propagation Delay (tPD)
Full
VI
3.2
4.3
3.2
4.3
ns
Rise Time (tR) (20% to 80%)
25°C
V
0.5
ns
Fall Time (tF) (20% to 80%)
25°C
V
0.5
ns
DCO Propagation Delay (tCPD)
Full
VI
1.8
2.7
3.8
1.8
2.7
3.8
ns
Data to DCO Skew (tPD – tCPD)
Full
IV
0.2
0.5
0.8
0.2
0.5
0.8
ns
Latency
Full
IV
14
Cycles
APERTURE DELAY (tA)
25°C
V
1.2
ns
APERTURE UNCERTAINTY (Jitter, tJ)
25°C
V
0.25
ps rms
OUT OF RANGE RECOVERY TIME (CMOS and LVDS)
25°C
V
1
Cycles
1 All ac specifications tested by differentially driving CLK+ and CLK.
2 DS inputs used in CMOS mode only.
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