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参数资料
| 型号： | AD9515BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIST 2OUT PLL 32LFCSP |
| 设计资源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 标准包装： | 1,500 |
| 类型： | 扇出缓冲器（分配），除法器 |
| PLL： | 无 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.6GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
| 配用： | AD9515/PCBZ-ND - BOARD EVAL CLOCK 2CH AD9515 |
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AD9515
Data Sheet
Rev. A | Page 18 of 28
FUNCTIONAL DESCRIPTION
OVERALL
The AD9515 provides for the distribution of its input clock on
one or both of its outputs. OUT0 is an LVPECL output. OUT1
can be set to either LVDS or CMOS logic levels. Each output
has its own divider that can be set for a divide ratio selected
from a list of integer values from 1 (bypassed) to 32.
OUT1 includes an analog delay block that can be set to add an
additional delay of 1.5 ns, 5 ns, or 10 ns full scale, each with
16 levels of fine adjustment.
CLK, CLKB—DIFFERENTIAL CLOCK INPUT
The CLK and CLKB pins are differential clock input pins.
This input works up to 1600 MHz. The jitter performance is
degraded by a slew rate below 1 V/ns. The input level should be
between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater can result in turning on the protection diodes
on the input pins.
See Figure 23 for the CLK equivalent input circuit. This
input is fully differential and self-biased. The signal should be
ac-coupled using capacitors. If a single-ended input must be
used, this can be accommodated by ac coupling to one side of
the differential input only. The other side of the input should be
bypassed to a quiet ac ground by a capacitor.
2.5k
5k
5k
2.5k
CLKB
CLK
VS
CLOCK INPUT
STAGE
05597-
021
Figure 23. Clock Input Equivalent Circuit
SYNCHRONIZATION
Power-On SYNC
A power-on sync (POS) is issued when the VS power supply is
turned on to ensure that the outputs start in synchronization.
The power-on sync works only if the VS power supply transi-
tions the region from 2.2 V to 3.1 V within 35 ms. The POS can
occur up to 65 ms after VS crosses 2.2 V. Only outputs which are
not divide = 1 are synchronized.
CLK
OUT
0V
3.3V
2.2V
3.1V
VS
CLOCK FREQUENCY
IS EXAMPLE ONLY
DIVIDE = 2
PHASE = 0
< 65ms
INTERNAL SYNC NODE
35ms
MAX
05597-094
Figure 24. Power-On Sync Timing
SYNCB
If the setup configuration of the AD9515 is changed during
operation, the outputs can become unsynchronized. The
outputs can be re-synchronized to each other at any time.
Synchronization occurs when the SYNCB pin is pulled low and
released. The clock outputs (except where divide = 1) are forced
into a fixed state (determined by the divide and phase settings)
and held there in a static condition, until the SYNCB pin is
returned to high. Upon release of the SYNCB pin, after four
cycles of the clock signal at CLK, all outputs continue clocking
in synchronicity (except where divide = 1).
When divide = 1 for an output, that output is not affected by
SYNCB.
CLK
SYNCB
OUT
3 CLK CYCLES
4 CLK CYCLES
EXAMPLE: DIVIDE
8
PHASE = 0
EXAMPLE DIVIDE
RATIO PHASE = 0
05597-093
Figure 25. SYNCB Timing with Clock Present
4 CLK CYCLES
CLK
OUT
SYNCB
DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO
§§§
§
DEPENDS ON PREVIOUS STATE
EXAMPLE DIVIDE
RATIO PHASE = 0
MIN 5ns
05597-092
Figure 26. SYNCB Timing with No Clock Present
The outputs of the AD9515 can be synchronized by using the
SYNCB pin. Synchronization aligns the phases of the clock
outputs, respecting any phase offset that has been set on an
output’s divider.
SYNCB
05597-
022
Figure 27. SYNCB Equivalent Input Circuit
相关PDF资料 |
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| AD9516-0BCPZ | IC CLOCK GEN 2.8GHZ VCO 64-LFCSP |
| AD9516-1BCPZ-REEL7 | IC CLOCK GEN 2.5GHZ VCO 64-LFCSP |
| AD9516-2BCPZ | IC CLOCK PLL/VCO 2.2GHZ 64LFCSP |
| AD9516-3BCPZ-REEL7 | IC CLOCK PLL/VCO 2GHZ 64LFCSP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD95160 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Channel Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0/PCBZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 64-LFCSP RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9516-0_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.8 GHz VCO |
| AD9516-0BCPZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 64-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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