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参数资料
型号： AD9516-3/PCBZ
厂商： Analog Devices Inc
文件页数： 3/80页
文件大小： 0K
描述： BOARD EVAL FOR AD9516-3 2.0GHZ
产品培训模块： Active Filter Design Tools
设计资源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-3 BOM
标准包装： 1
主要目的： 计时，时钟发生器
嵌入式： 否
已用 IC / 零件： AD9516-3
主要属性： 2 输入，14 输出，2GHz VCO
次要属性： CMOS、LVDS、LVPECL 输出逻辑，ADIsimCLK&trade 图形用户界面
已供物品： 板，线缆，CD，电源
产品目录页面： 776 (CN2011-ZH PDF)
相关产品： AD9516-3BCPZ-ND - IC CLOCK PLL/VCO 2GHZ 64LFCSP
AD9516-3BCPZ-REEL7-ND - IC CLOCK PLL/VCO 2GHZ 64LFCSP
Data Sheet
AD9516-3
Rev. C | Page 11 of 80
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
40
fs rms
BW = 12 kHz to 20 MHz
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
80
fs rms
BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
215
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
245
fs rms
Calculated from SNR of ADC method; DCC on
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
VCO Divider Not Used
85
fs rms
BW = 12 kHz to 20 MHz
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
113
fs rms
BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
280
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
365
fs rms
Calculated from SNR of ADC method; DCC not used
for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210
fs rms
Calculated from SNR of ADC method
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
285
fs rms
Calculated from SNR of ADC method
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
350
fs rms
Calculated from SNR of ADC method
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相关代理商/技术参数
参数描述
AD9516-4 制造商:AD 制造商全称:Analog Devices 功能描述:14-Output Clock Generator with Integrated 1.6 GHz VCO
AD9516-4/PCBZ 功能描述:BOARD EVAL FOR AD9516-4 1.8GHZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源
AD9516-4/PCBZ 制造商:Analog Devices 功能描述:AD9516-4, PLL CLOCK SYNTHESIZER, EVALUAT
AD9516-4BCPZ 功能描述:IC CLOCK GEN 1.6GHZ VCO 64-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND
AD9516-4BCPZ 制造商:Analog Devices 功能描述:CLOCK GENERATOR, 1.8GHZ, LFCSP-64
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