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| 型号： | AD9516-4BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 1.6GHZ VCO 64-LFCSP |
| 设计资源： | AD9516 Eval Brd Schematic AD9516 Gerber Files |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:14 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 产品目录页面： | 776 (CN2011-ZH PDF) |
| 配用： | AD9516-4/PCBZ-ND - BOARD EVAL FOR AD9516-4 1.8GHZ |
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Data Sheet
AD9516-4
Rev. C | Page 37 of 80
Holdover
The AD9516 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a state of high
impedance. This is useful when the PLL reference clock is lost.
Holdover mode allows the VCO to maintain a relatively constant
frequency even though there is no reference clock. Without this
function, the charge pump is placed into a constant pump-up or
pump-down state resulting in a massive VCO frequency shift.
Because the charge pump is placed in a high impedance state,
any leakage that occurs at the charge pump output or the VCO
tuning node causes a drift of the VCO frequency. This can be
mitigated by using a loop filter that contains a large capacitive
component because this drift is limited by the current leakage-
induced slew rate (ILEAK/C) of the VCO control voltage. For most
applications, the frequency accuracy is sufficient for 3 sec to 5 sec.
Both a manual holdover, using the SYNC pin, and an automatic
holdover mode are provided. To use either function, the
holdover function must be enabled (Register 0x01D[0] and
Register 0x01D[2]).
Note that the VCO cannot be calibrated with the holdover enabled
because the holdover resets the N divider during calibration,
which prevents proper calibration. Disable holdover before
issuing a VCO calibration.
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user
to place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state take the SYNC pin high. The charge pump then leaves
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state as long as there
is no reference clock present.
The B counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, set the channel dividers to ignore the
SYNC pin (at least after an initial SYNC event). If the dividers are
not set to ignore the SYNC pin, the distribution outputs turn off
each time SYNC is taken low to put the part into holdover.
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappears.
See Figure 53 for a flowchart of the internal/automatic holdover
function operation.
NO
YES
PLL ENABLED
DLD == LOW
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
HIGH IMPEDANCE
CHARGE PUMP
REFERENCE
EDGE AT PFD?
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
DLD == HIGH
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
REGISTER 0x1D[3] = 1: USE LD PIN
VOLTAGE WITH HOLDOVER.
REGISTER 0x1D[3] = 0: IGNORE LD PIN
VOLTAGE,TREAT LD PIN AS ALWAYS HIGH.
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
YES
06423-
069
Figure 53. Flowchart of Automatic/Internal Holdover Mode
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9516-4BCPZ | 制造商:Analog Devices 功能描述:CLOCK GENERATOR, 1.8GHZ, LFCSP-64 |
| AD9516-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.8GHZ VCO 64-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9516-5 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Output Clock Generator |
| AD9516-5/PCBZ | 功能描述:BOARD EVAL FOR AD9516-5 2.5GHZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9516-5BCPZ | 功能描述:IC CLOCK GEN W/PLL 64-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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