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参数资料
型号： AD9517-4ABCPZ-RL7
厂商： Analog Devices Inc
文件页数： 12/80页
文件大小： 0K
描述： IC CLOCK GEN 1.8GHZ VCO 48LFCSP
设计资源： High Performance, Dual Channel IF Sampling Receiver (CN0140)
标准包装： 750
类型： 时钟发生器，扇出配送
PLL： 是
输入： CMOS，LVDS，LVPECL
输出： CMOS，LVDS，LVPECL
电路数： 1
比率 - 输入:输出： 1:12
差分 - 输入:输出： 是/是
频率 - 最大： 1.8GHz
除法器/乘法器： 是/无
电源电压： 3.135 V ~ 3.465 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 48-VFQFN 裸露焊盘，CSP
供应商设备封装： 48-LFCSP-VQ（7x7）
包装： 带卷 (TR)
AD9517-4
Data Sheet
Rev. E | Page 2 of 80
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Power Supply Requirements ....................................................... 4
PLL Characteristics ...................................................................... 4
Clock Inputs .................................................................................. 6
Clock Outputs............................................................................... 6
Timing Characteristics ................................................................ 8
Clock Output Additive Phase Noise (Distribution Only;
VCO Divider Not Used).............................................................. 9
Clock Output Absolute Phase Noise (Internal VCO Used).. 10
Clock Output Absolute Time Jitter (Clock Generation
Using Internal VCO).................................................................. 11
Clock Output Absolute Time Jitter (Clock Cleanup
Using Internal VCO).................................................................. 11
Clock Output Absolute Time Jitter (Clock Generation
Using External VCXO) .............................................................. 11
Clock Output Additive Time Jitter (VCO Divider
Not Used)..................................................................................... 12
Clock Output Additive Time Jitter (VCO Divider Used) ..... 12
Delay Block Additive Time Jitter.............................................. 13
Serial Control Port ..................................................................... 13
PD, SYNC, and RESET Pins ..................................................... 14
LD, STATUS, and REFMON Pins............................................ 14
Power Dissipation....................................................................... 15
Timing Diagrams............................................................................ 16
Absolute Maximum Ratings.......................................................... 17
Thermal Resistance .................................................................... 17
ESD Caution................................................................................ 17
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 20
Terminology.................................................................................... 26
Detailed Block Diagram ................................................................ 27
Theory of Operation ...................................................................... 28
Operational Configurations...................................................... 28
Digital Lock Detect (DLD) ....................................................... 37
Clock Distribution ..................................................................... 41
Reset Modes ................................................................................ 49
Power-Down Modes .................................................................. 50
Serial Control Port ......................................................................... 51
Serial Control Port Pin Descriptions....................................... 51
General Operation of Serial Control Port............................... 51
The Instruction Word (16 Bits)................................................ 52
MSB/LSB First Transfers ........................................................... 52
Thermal Performance.................................................................... 55
Control Registers ............................................................................ 56
Control Register Map Overview .............................................. 56
Control Register Map Descriptions ......................................... 59
Applications Information .............................................................. 76
Frequency Planning Using the AD9517.................................. 76
Using the AD9517 Outputs for ADC Clock Applications.... 76
LVPECL Clock Distribution..................................................... 77
LVDS Clock Distribution.......................................................... 77
CMOS Clock Distribution ........................................................ 78
Outline Dimensions....................................................................... 79
Ordering Guide .......................................................................... 79
相关PDF资料
PDF描述
AD9518-0ABCPZ IC CLOCK GEN 6CH 2.8GHZ 48LFCSP
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