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| 型号： | AD9518-4ABCPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/64页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 带卷 (TR) |
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AD9518-4
Data Sheet
Rev. B | Page 14 of 64
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
SC
L
K
CS
SD
O
SD
IO
R
E
SET
PD
OU
T
4
OU
T
4
VS
_L
VP
E
C
L
OU
T
5
OU
T
5
VS
48
47
46
45
44
43
42
41
40
39
38
37
RE
F
IN
(
R
E
F
1)
RE
F
IN
(
R
E
F
2)
CP
RS
E
T
VS
RS
E
T
VS
OU
T0
OU
T0
VS
_L
VP
EC
L
OU
T1
OU
T1
VS
1
2
3
4
5
6
7
8
9
10
11
12
35
36
34
33
32
31
30
29
28
27
26
25
AD9518-4
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
CP
STATUS
CLK
VCP
REFMON
LD
BYPASS
VS
REF_SEL
LF
SYNC
CLK
OUT3
OUT2
VS
VS_LVPECL
OUT3
OUT2
NC
GND
VS
GND
06
43
3-
0
03
NOTES
1. NC = NO CONNECT.
2. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. Pin Configuration
Table 19. Pin Function Descriptions
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
1
I
3.3 V CMOS
REFMON
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 44,
Register 0x01B.
2
O
3.3 V CMOS
LD
Lock Detect (Output). This pin has multiple selectable outputs; see Table 44,
Register 0x01A.
3
I
Power
VCP
Power Supply for Charge Pump (CP). VS ≤ VCP ≤ 5.0 V. This pin is usually 3.3 V for most
applications; but if a 5 V external VCXO is used, this pin should be 5 V.
4
O
CP
Charge Pump (Output). Connects to external loop filter.
5
O
3.3 V CMOS
STATUS
Status (Output). This pin has multiple selectable outputs; see Table 44, Register 0x017.
6
I
3.3 V CMOS
REF_SEL
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
7
I
3.3 V CMOS
SYNC
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
8
I
Loop filter
LF
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has 31 pF of
internal capacitance to ground, which may influence the loop filter design for large
loop bandwidths.
9
O
Loop filter
BYPASS
This pin is for bypassing the LDO to ground with a capacitor.
10, 24, 25,
26, 35, 37,
43, 45
I
Power
VS
3.3 V Power Pins.
Along with CLK, this is the self-biased differential input for the clock distribution section.
This pin can be left floating if internal VCO is used.
11
I
Differential
clock input
CLK
12
I
Differential
clock input
CLK
Along with CLK, this is the self-biased differential input for the clock distribution section.
This pin can be left floating if internal VCO is used.
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