参数资料
型号: AD9520-3BCPZ-REEL7
厂商: Analog Devices Inc
文件页数: 1/80页
文件大小: 0K
描述: IC CLOCK GEN 2GHZ VCO 64LFCSP
设计资源: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
标准包装: 750
类型: 时钟发生器,扇出配送
PLL:
输入: CMOS,LVDS,LVPECL
输出: CMOS,LVPECL
电路数: 1
比率 - 输入:输出: 2:12,2:24
差分 - 输入:输出: 是/是
频率 - 最大: 2.25GHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
12 LVPECL/24 CMOS Output Clock
Generator with Integrated 2 GHz VCO
Data Sheet
Rev. A
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responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2008–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.72 GHz to 2.25 GHz
Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Automatic/manual reference holdover and reference
switchover modes, with revertive switching
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 3 outputs shares a 1-to-32 divider with
phase delay
Additive output jitter as low as 225 fs rms
Channel-to-channel skew grouped outputs < 16 ps
Each LVPECL output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual output synchronization available
SPI- and IC-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10GFC,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-31 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz
to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
FUNCTIONAL BLOCK DIAGRAM
OPTIONAL
REF1
REF2
CLK
LF
SW
IT
C
H
O
VER
AND
M
O
NI
T
O
R
PL
L
DIVIDER
AND MUXES
ZERO
DELAY
CP
VCO
STATUS
MONITOR
SPI/I2C CONTROL
PORT AND
DIGITAL LOGIC
EEPROM
AD9520
OUT0
OUT1
OUT2
DIV/Φ
OUT3
OUT4
OUT5
DIV/Φ
OUT6
OUT7
OUT8
DIV/Φ
OUT9
OUT10
OUT11
DIV/Φ
LVPECL/
CMOS
REFIN
07216-
001
Figure 1.
The AD9520 serial interface supports both SPI and IC ports.
An in-package EEPROM, which can be programmed through the
serial interface, can store user-defined register settings for
power-up and chip reset.
The AD9520 features 12 LVPECL outputs in four groups. Any
of the 1.6 GHz LVPECL outputs can be reconfigured as two
250 MHz CMOS outputs. If an application requires LVDS
drivers instead of LVPECL drivers, refer to the AD9522.
Each group of three outputs has a divider that allows both the
divide ratio (from 1 to 32) and the phase offset or coarse time
delay to be set.
The AD9520 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage of up to 5.5 V. A separate output driver power
supply can be from 2.375 V to 3.465 V.
The AD9520-3 is specified for operation over the standard
industrial range of 40°C to +85°C.
AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-3 is used, it refers to that specific member of the
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