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参数资料
| 型号： | AD9520-3BCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 75/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2GHZ VCO 64LFCSP |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 标准包装： | 750 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12，2:24 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD9520-3
Rev. A | Page 77 of 80
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9520
The AD9520 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9520, keep in mind the following
guidelines.
The AD9520 has four frequency dividers: the reference (or R)
divider, the feedback (or N) divider, the VCO divider, and the
channel divider. When trying to achieve a particularly difficult
frequency divide ratio requiring a large amount of frequency
division, some of the frequency division can be done by either
the VCO divider or the channel divider, thus allowing a higher
phase detector frequency and more flexibility in choosing the
loop bandwidth.
Within the AD9520 family, lower VCO frequencies generally
result in slightly better jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.4 GHz to 2.95 GHz) of the AD9520 family. If the desired
frequency plan can be achieved with a version of the AD9520
that has a lower VCO frequency, choosing the lower frequency
part results in the best phase noise and the lowest jitter. However,
choosing a higher VCO frequency can result in more flexibility
in frequency planning.
When determining a starting point, choosing a nominal charge
pump current in the middle of the allowable range allows the
designer to increase or decrease the charge pump current and,
thus, allows fine-tuning of the PLL loop bandwidth in either
direction.
Analog Devices has an AD9520 configuration tool that can
determine the best PLL configuration, based on the user’s input
and output frequencies. It can also design the loop filter based
on user requirements.
In addition to the configuration tool, ADIsimCLK is a powerful
PLL modeling tool and a very accurate tool for determining the
optimal loop filter for a given application.
USING THE AD9520 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the
AD9520 sampling clock. An ADC can be thought of as a sampling
mixer; and any noise, distortion, or time jitter on the clock is
combined with the desired signal at the analog-to-digital output.
Clock integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical SNR
of an ADC is limited by the ADC resolution and the jitter on the
sampling clock.
Considering an ideal ADC of infinite resolution where the step
size and quantization error can be ignored, the available SNR
can be expressed, approximately, by the following equation:
π
=
J
At
f
SNR
2
1
20log
(dB)
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 70 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
fA (MHz)
S
NR
(
d
B)
E
NO
B
10
1k
100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
t
J = 100f
s
t
J = 200f
s
t
J = 400f
s
t
J = 1p
s
t
J = 2p
s
t
J = 10p
s
SNR = 20log
1
2πfAtJ
07216-
044
Figure 70. SNR and ENOB vs. Analog Input Frequency
For more information, see the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter;
and the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sampling clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
The differential LVPECL outputs of the AD9520 enable clock
solutions that maximize converter SNR performance.
The input requirements of the ADC (differential or single-
ended, logic level termination) should be considered when
selecting the best clocking/converter solution.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9520-4BCPZ-REEL7 | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
| AD9520-5BCPZ-REEL7 | IC CLOCK GEN EXT VCO 64LFCSP |
| AD9522-0BCPZ-REEL7 | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| AD9522-1BCPZ-REEL7 | IC CLOCK GEN 2.5GHZ VCO 64LFCSP |
| AD9522-2BCPZ | IC CLOCK GEN 2.2GHZ VCO 64LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9520-4 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9520-4/PCBZ | 功能描述:BOARD EVAL FOR AD9520-4 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9520-4BCPZ | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9520-4BCPZ-REEL7 | 功能描述:IC CLOCK GEN 1.6GHZ VCO 64LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9520-5 | 制造商:AD 制造商全称:Analog Devices 功能描述:12 LVPECL/24 CMOS Output Clock Generator |
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