参数资料
| 型号： | AD9550BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N TRANSLATOR 32-LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟/频率转换器 |
| PLL： | 是 |
| 主要目的： | 以太网，GPON，SONET/SHD，T1/E1 |
| 输入： | CMOS |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 810MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ |
| 包装： | 托盘 |
AD9550
Rev. 0 | Page 12 of 20
THEORY OF OPERATION
PRECONFIGURED
DIVIDER SETTINGS
REF
A3 TO A0
4
CHARGE
PUMP
VCO
AD9550
OUT1
3350MHz TO
4050MHz
LOCKED
FILTER
P0
P2
P0
2
N
PF
D
LOCK
DETECT
OUT2
2
3
P2
10
DN
UP
LOOP
FILTER
OUTPUT
MODE
CONTROL
3
R
14
÷5
×2
÷5
÷5, ×2, R
PLL
Y5 TO Y0
6
OM2 TO
OM0
÷R
×2
1
0
1
0
N, P0, P1, P2
20
÷N
P1
10
09057-
019
Figure 23. Detailed Block Diagram
OVERVIEW
The AD9550 accepts one input reference clock, REF. The input
clock path includes an optional divide-by-5 prescaler, an optional
×2 frequency multiplier, and a 14-bit programmable divider (R).
The output of the R divider drives the input to the PLL.
The PLL translates the R-divider output to a frequency within
the operating range of the VCO (3.35 GHz to 4.05 GHz) based
on the value of the feedback divider (N). The VCO prescaler (P0)
reduces the VCO output frequency by an integer factor from 5 to 11,
resulting in an intermediate frequency in the range of 305 MHz
to 810 MHz. The 10-bit P1 and P2 dividers can further reduce
the P0 output frequency to yield the final output clock frequencies
at OUT1 and OUT2, respectively.
Thus, the frequency translation ratio from the reference input to
the output depends on the selection of the divide-by-5 prescalers,
the ×2 frequency multipliers, the values of the three R dividers,
the N divider, and the P0, P1, and P2 dividers. These parameters
are set automatically via the preconfigured divider settings per
the Ax and Yx pins (see the Preset Frequencies section).
PRESET FREQUENCIES
The frequency selection pins (A3 to A0 and Y5 to Y0) allow the
user to hardwire the device for preset input and output frequencies
based on the pin logic states (see Figure 23). The pins decode
ground or open connections as Logic 0 or Logic 1, respectively.
The A3 to A0 pins allow the user to select one of 15 input
reference frequencies as shown in Table 6. The device sets the
appropriate divide-by-5 (÷5), multiply-by-2 (×2), and input divider
(R) values based on the logic levels applied to the Ax pins.
The divide-by-5, ×2, and R values cause the PLL input frequency
to be either 16 kHz or 40/3 kHz. There are two exceptions. The
first is for A3 to A0 = 1101, which yields a PLL input frequency
of 155.52/59 MHz. The second is for A3 to A0 = 1110, which
yields a PLL input frequency of either 1.5625 MHz or 4.86 MHz
depending on the Y5 to Y0 pins.
The Y5 to Y0 pins allow the user to select one of 52 output frequency
appropriate P0, P1, and P2 settings based on the logic levels applied
to the Yx pins. Note, however, that selecting 101101 through
110010 require A3 to A0 = 1101 and selecting 110011 requires
A3 to A0 = 1110.
The value (N) of the PLL feedback divider and the control
setting for the charge pump current (CP) depend on a combi-
nation of both the Ax and Yx pin settings as shown in Table 8.
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