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参数资料
型号： AD9558BCPZ-REEL7
厂商： Analog Devices Inc
文件页数： 15/104页
文件大小： 0K
描述： IC CLK XLATR PLL 1250MHZ 64LFCSP
产品变化通告： AD9558 Minor Metal Mask Change 17/Apr/2012
标准包装： 750
类型： 时钟/频率转换器
PLL： 是
主要目的： 以太网，SONET/SDH，Stratum
输入： CMOS，LVDS，LVPECL
输出： CMOS，HSTL，LVDS
电路数： 1
比率 - 输入:输出： 4:6
差分 - 输入:输出： 是/是
频率 - 最大： 1.25GHz
电源电压： 1.71 V ~ 3.465 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-VFQFN 裸露焊盘，CSP
供应商设备封装： 64-LFCSP-VQ（9x9）
包装： 带卷 (TR)
AD9558
Data Sheet
Rev. B | Page 18 of 104
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
13
AA
OUT4
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 4. This output can be configured as HSTL, LVDS, or single-ended
1.8 V CMOS.
14
OUT4
O
HSTL, LVDS,
or 1.8 V CMOS
Output 4. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
15
AA
OUT3
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 3. This output can be configured as HSTL, LVDS,
or single-ended 1.8 V CMOS.
16
OUT3
O
HSTL, LVDS, or
1.8 V CMOS
Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
18
AA
OUT2
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 2. This output can be configured as HSTL, LVDS, or
single-ended 1.8 V CMOS.
19
OUT2
O
HSTL, LVDS, or
1.8 V CMOS
Output 2. This output can be HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
20
AA
OUT1
EE
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 1. This output can be configured as HSTL, LVDS, or
single-ended 1.8 V CMOS.
21
OUT1
O
HSTL, LVDS,
or 1.8 V CMOS
Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations section.
23
AA
OUT5
EE
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Complementary Output 5. This output can be configured as HSTL, LVDS, or single-ended
1.8 V or 3.3 V CMOS.
24
OUT5
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Output 5. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V
CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-
equivalent termination as described in the Input/Output Termination
Recommendations section.
25, 26
AVDD3
I
Power
3.3 V Analog (Output Driver) Power Supply.
27
AA
OUT0
EE
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Complementary Output 0. This output can be configured as HSTL, LVDS, or single-
ended 1.8 V or 3.3 V CMOS.
28
OUT0
O
HSTL, LVDS,
1.8 V CMOS,
3.3 V CMOS
Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V
CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-
equivalent termination as described in the Input/Output Termination
Recommendations section.
31
AVDD3
I
Power
3.3V Analog (VCO 2) Power Supply.
32
LDO_VCO2
I
LDO bypass
Output PLL Loop Filter Voltage Regulator. Connect a 0.47 μF capacitor from this pin
to ground. This pin is also the ac ground reference for the integrated output PLL
external loop filter.
33
LF_VCO2
I/O
Loop filter
Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from this
pin to Pin 32 (LDO_VCO2).
34
NC
No Connect. There is no internal connection for this pin.
35
AVDD
I
Power
1.8 V Analog (APLL) Power Supply.
36
NC
No Connect. There is no internal connection for this pin.
37, 38
AVDD
I
Power
1.8 V Analog (DCO and TDC) Power Supplies.
39
AA
RESET
EE
I
3.3 V CMOS
Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has
an internal 50 k pull-up resistor.
40
PINCONTROL
I
3.3 V CMOS
Pin Program Mode Enable Pin. When pulled high during startup, this pin enables pin
programming of the AD9558 configuration during startup. If this pin is low during
startup, the user must program the part via the serial port, or use values that are
stored in the EEPROM.
41
M7
I/O
3.3 V CMOS
Configurable I/O Pin. Along with pins M6 through M0, this pin is configured through
the AD9558 register space.
42
AA
SYNC
EE
I
3.3 V CMOS
Clock Distribution Synchronization Pin. When this pin is activated, output drivers are
held static and then synchronized on a low-to-high transition of this pin. This pin is
used to arm the frame sync function when frame sync mode is enabled and has an
internal 60 k pull-up resistor.
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