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参数资料
| 型号： | AD9572ACPZPEC-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 40LFCSP |
| 标准包装： | 2,500 |
| 类型： | 时钟发生器，扇出配送，多路复用器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:7 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.97 V ~ 3.63 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 带卷 (TR) |
AD9572
Rev. B | Page 20 of 20
OUTLINE DIMENSIONS
0
2-02-2010-
A
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
EXPOSED
PAD
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
0.80
0.75
0.70
FORPROPERCONNECTIONOF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.45
0.40
0.35
0.20 MIN
*4.70
4.60 SQ
4.50
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
40
1
11
20
21
30
31
10
Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-7)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature Range
Package Description
Package Option
AD9572ACPZLVD
40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-40-7
AD9572ACPZLVD-RL
40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
13”Tape and Reel, 2,500 Pieces
CP-40-7
AD9572ACPZLVD-R7
40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
7”Tape and Reel, 750 Pieces
CP-40-7
AD9572ACPZPEC
40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-40-7
AD9572ACPZPEC-RL
40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
13”Tape and Reel, 2,500 Pieces
CP-40-7
AD9572ACPZPEC-R7
40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
7”Tape and Reel, 750 Pieces
CP-40-7
AD9572-EVALZ-LVD
Evaluation Board
AD9572-EVALZ-PEC
Evaluation Board
1 Z = RoHS Compliant Part.
2 LVD indicates LVDS-compliant, differential clock outputs.
3 PEC indicates LVPECL-compliant, differential clock outputs.
2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07498-0-4/11(B)
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| AD9571ACPZPEC-RL | IC PLL CLOCK GEN 25MHZ 40LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9572-EVALZ-LVD | 制造商:AD 制造商全称:Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs |
| AD9572-EVALZ-PEC | 制造商:AD 制造商全称:Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs |
| AD9572XCPZLVD | 制造商:Analog Devices 功能描述: |
| AD9572XCPZPEC | 制造商:Analog Devices 功能描述: |
| AD9573 | 制造商:AD 制造商全称:Analog Devices 功能描述:PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs |
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