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参数资料
| 型号： | AD9573ARUZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC PCI CLCOK GEN 25MHZ 16TSSOP |
| 标准包装： | 1,000 |
| 系列： | PCI Express® (PCIe) |
| 类型： | 时钟/频率发生器，扇出缓冲器（分配） |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 输入： | 晶体 |
| 输出： | LVCMOS，LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 100MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
AD9573
Rev. 0 | Page 8 of 12
TERMINOLOGY
Phase Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 degrees to
360 degrees for each cycle. Actual signals, however, display a
certain amount of variation from ideal phase progression over
time. This phenomenon is called phase jitter. Although many
causes can contribute to phase jitter, one major cause is random
noise, which is characterized statistically as gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
Phase Noise
When the total power contained within some interval of offset
frequencies (for example, 12 kHz to 20 MHz) is integrated, it is
called the integrated phase noise over that frequency offset
interval, and it can be readily related to the time jitter due to the
phase noise within that offset frequency interval.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings is seen to vary.
In a square wave, the time jitter is seen as a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the gaussian distribution.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is
attributable to the device or subsystem being measured. The
time jitter of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system time jitter when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own time jitter to the total. In many
cases, the time jitter of the external oscillators and clock sources
dominates the system time jitter.
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相关代理商/技术参数 |
参数描述 |
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| AD9573-EVALZ | 制造商:AD 制造商全称:Analog Devices 功能描述:PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs |
| AD9574BCPZ | 功能描述:IC PLL CLOCK GEN 25MHZ 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:有效 类型:* PLL:带旁路 输入:时钟 输出:CMOS，HCSL，HSTL，LVDS 电路数:1 比率 - 输入:输出:2：7 差分 - 输入:输出:是/是 频率 - 最大值:312.5MHz 分频器/倍频器:是/是 电压 - 电源:2.97 V ~ 3.63 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘，CSP 供应商器件封装:48-LFCSP-WQ（7x7） 标准包装:1 |
| AD9574BCPZ-REEL7 | 功能描述:IC PLL CLOCK GEN 25MHZ 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 类型:* PLL:带旁路 输入:时钟 输出:CMOS，HCSL，HSTL，LVDS 电路数:1 比率 - 输入:输出:2：7 差分 - 输入:输出:是/是 频率 - 最大值:312.5MHz 分频器/倍频器:是/是 电压 - 电源:2.97 V ~ 3.63 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘，CSP 供应商器件封装:48-LFCSP-WQ（7x7） 标准包装:750 |
| AD9575 | 制造商:AD 制造商全称:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
| AD9575ARUZLVD | 功能描述:IC PLL CLOCK GEN 25MHZ 16TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:PCI Express® (PCIe) 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
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