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参数资料
| 型号： | AD9633BCPZ-125 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/40页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 125MSPS 48LFCSP |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 125M |
| 数据接口： | LVDS，串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 526mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-WQ（7x7） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个差分，双极 |
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Data Sheet
AD9633
Rev. 0 | Page 37 of 40
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Device Index (Register 0x05)
There are certain features in the map that can be set
independently for each channel, whereas other features apply
globally to all channels (depending on context) regardless of
which are selected. The first four bits in Register 0x05 can be
used to select which individual data channels are affected. The
output clock channels can be selected in Register 0x05 as well. A
smaller subset of the independent feature list can be applied to
those devices.
Transfer (Register 0xFF)
All registers except Register 0x100 are updated the moment
they are written. Setting Bit 0 of this transfer register high
initializes the settings in the ADC sample rate override register
(Address 0x100).
Power Modes (Register 0x08)
Bits[7:6]—Open
Bit 5—External Power-Down Pin Function
If set, the external PDWN pin initiates power-down mode.
If cleared, the external PDWN pin initiates standby mode.
Bits[4:2]—Open
Bits[1:0]—Power Mode
In normal operation (Bits[1:0] = 00), all ADC channels are
active.
In power-down mode (Bits[1:0] = 01), the digital datapath clocks
are disabled while the digital datapath is reset. Outputs are
disabled.
In standby mode (Bits[1:0] = 10), the digital datapath clocks
and the outputs are disabled.
During a digital reset (Bits[1:0] = 11), all the digital datapath
clocks and the outputs (where applicable) on the chip are reset,
except the SPI port. Note that the SPI is always left under
control of the user; that is, it is never automatically disabled or
in reset (except by power-on reset).
Enhancement Control (Register 0x0C)
Bits[7:3]—Open
Bit 2—Chop Mode
For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct conversion
receivers, chopping in the first stage of the AD9633 is a feature
that can be enabled by setting Bit 2. In the frequency domain,
chopping translates offsets and other low frequency noise to
fCLK/2 where it can be filtered.
Bits[1:0]—Open
Output Mode (Register 0x14)
Bit 7—Open
Bit 6—LVDS-ANSI/LVDS-IEEE Option
Setting this bit chooses LVDS-IEEE (reduced range) option.
The default setting is LVDS-ANSI. As described in Table 18,
when LVDS-ANSI or LVDS-IEEE reduced range link is selected,
the user can select the driver termination. The driver current
is automatically selected to give the proper output swing.
Table 18. LVDS-ANSI/LVDS-IEEE Options
Output
Mode,
Bit 6
Output
Mode
Output
Driver
Termination
Output Driver
Current
0
LVDS-ANSI
User
selectable
Automatically
selected to give
proper swing
1
LVDS-IEEE
reduced
range link
User
selectable
Automatically
selected to give
proper swing
Bits[5:3]—Open
Bit 2—Output Invert
Setting this bit inverts the output bit stream.
Bit 1—Open
Bit 0—Output Format
By default, this bit is set to send the data output in twos
complement format. Resetting this bit changes the output mode
to offset binary.
Output Adjust (Register 0x15)
Bits[7:6]—Open
Bits[5:4]—Output Driver Termination
These bits allow the user to select the internal termination
resistor.
Bits[3:1]—Open
Bit 0—Output Drive
Bit 0 of the output adjust register controls the drive strength on the
LVDS driver of the FCO and DCO outputs only. The default
values set the drive to 1× while the drive can be increased to 2× by
setting the appropriate channel bit in Register 0x05 and then
setting Bit 0. These features cannot be used with the output
driver termination select. The termination selection takes prece-
dence over the 2× driver strength on FCO and DCO when both
the output driver termination and output drive are selected.
Output Phase (Register 0x16)
Bit 7—Open
Bits[6:4]—Input Clock Phase Adjust
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相关代理商/技术参数 |
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| AD9633BCPZ-80 | 功能描述:IC ADC 12BIT SRL 80MSPS 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD9633BCPZRL7-105 | 功能描述:IC ADC 12BIT SRL 105MSPS 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9633BCPZRL7-125 | 功能描述:模数转换器 - ADC 12 bit 125msps low pwr quad ADC RoHS:否 制造商:Analog Devices 通道数量: 结构: 转换速率: 分辨率: 输入类型: 信噪比: 接口类型: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
| AD9633BCPZRL7-80 | 功能描述:IC ADC 12BIT SRL 80MSPS 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9634 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit, 170 MSPS/210 MSPS/250 MSPS |
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