参数资料
型号: AD9717BCPZRL7
厂商: Analog Devices Inc
文件页数: 4/80页
文件大小: 0K
描述: IC DAC DUAL 14BIT LO PWR 40LFCSP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 750
系列: TxDAC®
位数: 14
数据接口: 串行
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 86mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 带卷 (TR)
输出数目和类型: 4 电流,单极
采样率(每秒): 125M
AD9714/AD9715/AD9716/AD9717
Rev. A | Page 12 of 80
07
26
5-
06
7
PIN 1
INDICATOR
1
DB7
2
DB6
3
DB5
4
DB4
5
DVDDIO
6
DVSS
7
DVDD
8
DB3
9
DB2
10
DB1
23 QOUTP
24 RLQP
25 AVSS
26 AVDD
27 RLIP
28 IOUTP
29 IOUTN
30 RLIN
22 QOUTN
21 RLQN
11
D
B
0
(L
S
B
)
12
N
C
13
N
C
15
N
C
17
C
V
D
16
D
C
L
K
IO
18
C
L
K
IN
19
C
V
S
20
C
M
L
Q
14
N
C
33
F
S
A
D
JI
/A
U
X
I
34
R
E
F
IO
35
R
E
S
E
T
/P
IN
M
D
36
S
C
L
K
/C
L
K
M
D
37
S
D
IO
/F
O
R
M
A
T
38
39
D
B
9
(M
S
B
)
40
D
B
8
32
F
S
A
D
JQ
/A
U
X
Q
31
C
M
L
I
TOP VIEW
(Not to Scale)
AD9715
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
C
S
/P
W
R
D
N
Figure 3. AD9715 Pin Configuration
Table 8. AD9715 Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
DB[7:4]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
6
DVSS
Digital Common.
7
DVDD
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 μF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 10
DB[3:1]
Digital Inputs.
11
DB0 (LSB)
Digital Input (LSB).
12 to 15
NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
21
RLQN
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
24
RLQP
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
Analog Supply Voltage (1.8 V to 3.3 V).
27
RLIP
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
30
RLIN
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
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