参数资料
| 型号： | AD9742ARUZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 210MSPS 28-TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 系列： | TxDAC® |
| 设置时间： | 11ns |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 145mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 210M |
| 配用： | AD9742ACP-PCBZ-ND - BOARD EVAL FOR AD9742ACP |
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Data Sheet
AD9742
Rev. C | Page 15 of 32
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship
between the position of the clock edges and the time at which
the input data changes. The AD9742 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when applying
the AD9742 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 27 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement,
while at higher rates, more care must be taken.
–3
–2
2
–1
0
1
65
75
ns
dB
3
55
45
35
60
70
50
40
50MHz SFDR
20MHz SFDR
50MHz SFDR
02912-B-026
Figure 27. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz
Sleep Mode Operation
The AD9742 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and temperature
range. This mode can be activated by applying a Logic Level 1
to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5
AVDD. This digital input also contains an active pull-down circuit
that ensures that the AD9742 remains enabled if this input is
left disconnected. The AD9742 takes less than 50 ns to power
down and approximately 5 s to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9742 is dependent on several
factors that include:
The power supply voltages (AVDD, CLKVDD, and DVDD)
The full-scale current output IOUTFS
The update rate fCLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly
fCLOCK. Conversely, IDVDD is dependent on both the digital input
IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
IOUTFS (mA)
35
0
2
I AVDD
(mA)
30
25
20
15
10
4
6
8
10
12
14
16
18
20
02912-B-027
Figure 28. IAVDD vs. IOUTFS
RATIO (fOUT/fCLOCK)
20
0.01
1
0.1
I DVDD
(mA)
18
16
14
12
10
8
6
4
2
0
165MSPS
125MSPS
65MSPS
02912-B-028
210MSPS
Figure 29. IDVDD vs. Ratio @ DVDD = 3.3 V
0
50
250
100
150
200
0
2
4
6
8
12
10
fCLOCK (MSPS)
I
CLKVDD
(mA)
DIFF
PECL
SE
02912-B-029
Figure 30. ICLKVDD vs. fCLOCK and Clock Mode
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9742ARZ | 功能描述:IC DAC 12BIT 210MSPS 28-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD9742ARZRL | 功能描述:IC DAC 12BIT 210MSPS 28-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD9742-EB | 制造商:Analog Devices 功能描述:EVAL BOARDFOR AD9742 - Bulk |
| AD9742-EBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit, 210 MSPS TxDAC Digital-to-Analog Converter |
| AD9743 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters |
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