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参数资料
| 型号： | AD9746-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 14BIT 72LFCSP |
| 设计资源： | AD9747/6/5/3/1 DPG2 Eval Brd Schematic |
| 标准包装： | 1 |
| DAC 的数量： | 2 |
| 位数： | 14 |
| 采样率（每秒）： | 250M |
| 数据接口： | 并联 |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9746 |
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AD9741/AD9743/AD9745/AD9746/AD9747
Data Sheet
Rev. A | Page 24 of 28
DAC TRANSFER FUNCTION
IOUTP provides a near full-scale current output (IFS) when all bits
are high. For example,
DAC CODE = 2N 1
where:
The current output appearing at IOUTP and IOUTN is a function of
both the input code and IFS and can be expressed as
IOUTP = (DAC DATA/2N) × IFS
(1)
IOUTN = ((2N 1) DAC DATA)/2N × IFS
(2)
where DAC DATA = 0 to 2N 1 (decimal representation).
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTP and IOUTN
should be connected to matching resistive loads (RLOAD) that are
tied to analog common (AVSS). The single-ended voltage
output appearing at the IOUTP and IOUTN pins is
VOUTP = IOUTP × RLOAD
(3)
VOUTN = IOUTN × RLOAD
(4)
Note that to achieve the maximum output compliance of 1 V at
the nominal 20 mA output current, RLOAD must be set to 50 Ω.
Also note that the full-scale value of VOUTP and VOUTN should
not exceed the specified output compliance range to maintain
specified distortion and linearity performance.
There are two distinct advantages to operating the AD9741/
ential operation helps cancel common-mode error sources
associated with IOUTP and IOUTN, such as noise, distortion, and
dc offsets. Second, the differential code dependent current
and subsequent output voltage (VDIFF) is twice the value of the
single-ended voltage output (VOUTP or VOUTN), providing 2×
signal power to the load.
VDIFF = (IOUTP – IOUTN) × RLOAD
(5)
ANALOG MODES OF OPERATION
proprietary quad-switch architecture that lowers the distortion
of the DAC output by eliminating a code dependent glitch that
occurs with conventional dual-switch architectures. But whereas
this architecture eliminates the code dependent glitches, it creates
a constant glitch at a rate of 2 × fDAC. For communications
systems and other applications requiring good frequency
domain performance, this is seldom problematic.
The quad-switch architecture also supports two additional
modes of operation; mix mode and return-to-zero (RZ) mode.
The waveforms of these two modes are shown in Figure 35. In
mix mode, the output is inverted every other half clock cycle.
This effectively chops the DAC output at the sample rate. This
chopping has the effect of frequency shifting the sinc roll-off
from dc to fDAC. Additionally, there is a second subtle effect on
the output spectrum. The shifted spectrum is shaped by a second
sinc function with a first null at 2 × fDAC. The reason for this
shaping is that the data is not continuously varying at twice the
clock rate, but is simply repeated.
In RZ mode, the output is set to midscale on every other half
clock cycle. The output is similar to the DAC output in normal
mode except that the output pulses are half the width and half
the area. Because the output pulses have half the width, the
sinc function is scaled in frequency by 2 and has a first null at
2 × fDAC. Because the area of the pulses is half that of the pulses
in normal mode, the output power is half the normal mode
output power.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D10
INPUT DATA
DAC CLK
4-SWITCH
DAC OUTPUT
(
fS MIX MODE)
4-SWITCH
DAC OUTPUT
(RETURN TO
ZERO MODE)
06569-
026
t
Figure 35. Mix Mode and RZ Mode DAC Waveforms
The functions that shape the output spectrums for normal mode,
mix mode, and RZ mode, are shown in Figure 36. Switching
between the modes reshapes the sinc roll off inherent at the
DAC output. This ability to change modes in the AD9741/
direct IF applications. The user can place a carrier anywhere in
the first three Nyquist zones depending on the operating mode
selected. The performance and maximum amplitude in all three
zones are impacted by this sinc roll off depending on where the
carrier is placed, as shown in Figure 36.
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