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参数资料
| 型号： | AD9746-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 14BIT 72LFCSP |
| 设计资源： | AD9747/6/5/3/1 DPG2 Eval Brd Schematic |
| 标准包装： | 1 |
| DAC 的数量： | 2 |
| 位数： | 14 |
| 采样率（每秒）： | 250M |
| 数据接口： | 并联 |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9746 |
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AD9741/AD9743/AD9745/AD9746/AD9747
Data Sheet
Rev. A | Page 25 of 28
0
–10
–20
–30
–40
T
(f)
(d
B
)
0.5
1.5
2
FS
NORMAL
RZ
MIX
06569-
027
Figure 36. Transfer Function for Each Analog Operating Mode
AUXILIARY DACS
in Figure 37. The auxiliary DACs are current output devices
with two output pins, AUXP and AUXN. The active pin can
be programmed to either source or sink current. When either
sinking or sourcing, the full-scale current magnitude is 2 mA.
The available compliance range at the auxiliary DAC outputs
depends on whether the output is configured to a sink or source
current. When sourcing current, the compliance voltage is 0 V
to 1.6 V, but when sinking current, the output compliance
voltage reduces to 0.8 V to 1.6 V. Either output can be used, but
only one output of the auxiliary DAC (P or N) is active at any
time. The inactive pin is always in a high impedance state
(>100 kΩ).
06569-
035
VBIAS
AUXP
AUXN
SINK
OR
SOURCE
POSITIVE
OR
NEGATIVE
0mA
TO
2mA
0mA
TO
2mA
Figure 37. Auxiliary DAC Functional Diagram
In a single side band transmitter application, the combination of
the input referred dc offset voltage of the quadrature modulator
and the DAC output offset voltage can result in local oscillator
(LO) feedthrough at the modulator output, which degrades
system performance. The auxiliary DACs can be used to remove
the dc offset and the resulting LO feedthrough. The circuit
configuration for using the auxiliary DACs for performing
dc offset correction depends on the details of the DAC and
modulator interface. An example of a dc-coupled configuration
with low-pass filtering is outlined in the Power Dissipation
section.
AD9747
AUX
DAC1 OR
DAC2
AD9747
DAC1 OR
DAC2
25 TO 50
QUAD MOD
I OR Q INPUTS
QUADRATURE
MODULATOR V+
25 TO 50
06569-
029
OPTIONAL
PASSIVE
FILTERING
Figure 38. DAC DC Coupled to Quadrature Modulator with Passive DC Shift
POWER DISSIPATION
Figure 39 shows the power dissipation and current draw of the
devices have a quiescent power dissipation of about 190 mW.
Most of this comes from the AVDD33 supply. Total power
dissipation increases about 50% as the clock rate is increased
to the maximum clock rate of 250 MHz.
350
310
270
230
190
150
P
TO
TA
L
(
mW
)
0
50
100
150
200
250
fDAC (MHz)
06569-
030
25
75
125
175
225
fOUT = DC
fOUT = NYQUIST
Figure 39. AD9747 Power Dissipation vs. fDAC
15
12
9
6
3
0
I DV
DD3
3
(
mA)
0
50
100
150
200
250
fDAC (MHz)
06569-
031
25
75
125
175
225
AD9747
AD9741
Figure 40. DVDD33 Current vs. fDAC
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