参数资料
| 型号： | AD9753ASTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 300MSPS 48-LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| 设置时间： | 11ns |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 165mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 300M |
| 配用： | AD9753-EB-ND - BOARD EVAL FOR AD9753 |
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REV. B
AD9753
–15–
DVDD
DIGITAL
INPUT
Figure 14. Equivalent Digital Input
The AD9753 features a flexible differential clock input operat-
ing from separate supplies (i.e., CLKVDD, CLKCOM) to
achieve optimum jitter performance. The two clock inputs,
CLK+ and CLK–, can be driven from a single-ended or differ-
ential clock source. For single-ended operation, CLK+ should
be driven by a logic source while CLK– should be set to the
threshold voltage of the logic source. This can be done via a
resistor divider/capacitor network, as shown in Figure 15a. For
differential operation, both CLK+ and CLK– should be biased to
CLKVDD/2 via a resistor divider network, as shown in Figure 15b.
RSERIES
0.1 F
VTHRESHOLD
CLK+
CLKVDD
CLK–
CLKCOM
AD9753
Figure 15a. Single-Ended Clock Interface
0.1 F
CLK+
CLKVDD
CLK–
CLKCOM
AD9753
0.1 F
Figure 15b. Differential Clock Interface
Because the output of the AD9753 can be updated at up to
300 MSPS, the quality of the clock and data input signals is
important in achieving the optimum performance. The drivers
of the digital data interface circuitry should be specified to
meet the minimum setup-and-hold times of the AD9753 as
well as its required min/max input logic level thresholds.
Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. Inserting a low value resis-
tor network (i.e., 20
to 100 ) between the AD9753 digital
inputs and driver outputs may be helpful in reducing any over-
shooting and ringing at the digital inputs that contribute to data
feedthrough. For longer run lengths and high data update rates,
strip line techniques with proper termination resistors should be
considered to maintain “clean” digital inputs.
The external clock driver circuitry should provide the AD9753
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges help minimize any
jitter that will manifest itself as phase noise on a reconstructed
waveform. Thus, the clock input should be driven by the fastest
logic family suitable for the application.
Note that the clock input could also be driven via a sine wave
that is centered around the digital threshold (i.e., DVDD/2) and
meets the min/max logic threshold. This typically results in a
slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies. Also,
at higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and, subsequently, cut into the required data
setup-and-hold times.
INPUT CLOCK AND DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9753 is rising edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9753 is to
make the data transition close to the falling clock edge. This
becomes more important as the sample rate increases. Figure 16
shows the relationship of SNR to clock placement with different
sample rates. Note that the setup-and-hold times implied in
Figure 16 appear to violate the maximums stated in the Digital
Specifications of this data sheet. The variation in Figure 16 is
due to the skew present between data bits inherent in the digital
data generator used to perform these tests. Figure 16 is presented
to show the effects of violating setup-and-hold times and to
show the insensitivity of the AD9753 to clock placement when
data transitions fall outside of the so-called “bad window.” The
setup-and-hold times stated in the Digital Specifications table
were measured on a bit-by-bit basis, therefore eliminating the
skew present in the digital data generator. At higher data
rates, it becomes very important to account for the skew in
the input digital data when defining timing specifications.
TIME OF DATA TRANSITION RELATIVE TO PLACEMENT OF
CLK RISING EDGE (ns), fOUT = 10MHz, fDAC = 300MHz
80
40
0
3
0
–3
SNR
(dBc)
60
20
70
30
50
10
–2
–1
1
2
Figure 16. SNR vs. Time of Data Transition
Relative to Clock Rising Edge
POWER DISSIPATION
The power dissipation, PD, of the AD9753 is dependent on several
factors that include the power supply voltages (AVDD and
DVDD), the full-scale current output IOUTFS, the update rate
fCLOCK, and the reconstructed digital input waveform. The
power dissipation is directly proportional to the analog sup-
ply current, IAVDD, and the digital supply current, IDVDD.
IAVDD is directly proportional to IOUTFS, as shown in Figure 17,
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9753ASTZRL | 功能描述:IC DAC 12BIT 300MSPS 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9753-EB | 功能描述:BOARD EVAL FOR AD9753 RoHS:否 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9754 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9754AR | 功能描述:IC DAC 14BIT 125MSPS HP 28-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
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