参数资料
| 型号： | AD9761ARSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT DUAL 40MSPS 28-SSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 47 |
| 设置时间： | 35ns |
| 位数： | 10 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 250mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 管件 |
| 输出数目和类型： | 4 电流，单极；4 电流，双极 |
| 采样率（每秒）： | 40M |
| 产品目录页面： | 785 (CN2011-ZH PDF) |
| 配用： | AD9761-EBZ-ND - BOARD EVAL FOR AD9761 |
AD9761
–12–
AD9761
–13–
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from
its nominal 1.25 V for an IOUTFS = 10 mA to 1.00 V for an
IOUTFS = 2 mA. Applications requiring the AD9761’s output
(i.e., VOUTA and/or VOUTB) to extend to its output compliance
range should size RLOAD accordingly. Operation beyond this
compliance range will adversely affect the AD9761’s linearity
performance and subsequently degrade its distortion perfor-
mance. Note that the optimum distortion performance of
the AD9761 is obtained by restricting its output(s) as seen at
IOUT(A/B) and QOUT(A/B) to within ±0.5 V.
DIGITAL INPUTS AND INTERLEAVED INTERFACE
CONSIDERATIONS
The AD9761 digital interface consists of 10 data input pins,
a clock input pin, and three control pins. It is designed to
support a clock rate up to 40 MSPS. The 10-bit parallel
data inputs follow standard positive binary coding, where
DB9 is the most significant bit (MSB) and DB0 is the
least significant bit (LSB). IOUTA (or QOUTA) produces
a full-scale output current when all data bits are at Logic 1.
IOUTB (or QOUTB) produces a complementary output,
with the full-scale current split between the two outputs as a
function of the input code.
STATE
MACHINE
I AND Q DATA
CLOCK
SELECT
RESET/SLEEP
WRITE
Q DATA
CLOCK
2
I DATA
I
INPUT
REGISTER
I
FILTER
REGISTER
Q
INPUT
REGISTER
Q
INPUT
REGISTER
Figure 10. Block Diagram of Digital Interface
The AD9761 interfaces with a single 10-bit digital input
bus that supports interleaved I and Q input data. Figure 10
shows a simplified block diagram of the digital interface
circuitry consisting of two banks of edge triggered registers,
two multiplexers, and a state machine. Interleaved I and Q
input data is presented at the DATA input bus, where it is
then latched into the selected I or Q input register on the
rising edge of the WRITE input. The output of these input
registers is transferred in pairs to their respective interpola-
tor filters’ register after each Q write on the rising edge of
the CLOCK input (refer to Timing Diagram in Figure 1).
A state machine ensures the proper pairing of I and Q input
data to the interpolation filter’s inputs.
The SELECT signal at the time of the rising edge of the
WRITE signal determines which input register latches
the input data. If SELECT is high around the rising
edge of WRITE, the data is latched into the I register of
the AD9761. If SELECT is low around the rising edge
of WRITE, the data is latched into the Q register of the
AD9761. If SELECT is kept in one state while data is
repeatedly writing to the AD9761, the data will be written
into the selected filter register at half the input data rate
since the data is always assumed to be interleaved.
The state machine controls the generation of the divided
clock and thus pairing of I and Q data inputs. After the
AD9761 is reset, the state machine keeps track of the paired
I and Q data. The state transition diagram is shown in Fig-
ure 11, in which all states are defined. A transition in state
occurs upon the rising edge of CLOCK and is a function
of the current state as well as status of SELECT, WRITE,
and SLEEP. The state machine is reset on the first rising
CLOCK edge while RESET remains high. Upon RESET
returning low, a state transition will occur on the first rising
edge of CLOCK. The most recent I and Q data samples
are transferred to the correct interpolation filter only upon
entering state FILTER DATA.
Note that it is possible to ensure proper pairing of I and Q data
inputs without issuing RESET high. This may be accomplished
by writing two or more successive Q data inputs followed by
a clock. In this case, the state machine will advance to either
the RESET or FILTER DATA state. The state machine
will advance to the ONE-I state upon writing I data followed
by a clock.
ONE, I
RESET
FILTER
DATA
I or Q or N
N
I = WRITE AND SELECT FOLLOWED BY A CLOCK
Q = WRITE AND SELECT FOLLOWED BY A CLOCK
N = CLOCK ONLY, NO WRITE
I
Q
Q or N
Figure 11. StateTransition Diagram of AD9761
Digital Interface
An example helps illustrate the digital timing and control
requirements to ensure proper pairing of I and Q data. In
this example, the AD9761 is assumed to interface with a host
processor on a dedicated data bus and the state machine
is reset by asserting a Logic Level 1 to the RESET/SLEEP
input for a duration of one clock cycle. In the timing diagram
shown in Figure 12, WRITE and CLOCK are tied together
while SELECT is updated at the same instance as DATA.
Since SELECT is high upon RESET returning low, I data is
latched into the I input register on the first rising WRITE.
On the next rising WRITE edge, the Q data is latched into
its input register and the outputs of both input registers are
latched into their respective I and Q filter registers. The
sequence of events is repeated on the next rising WRITE edge
with the new I data being latched into the I input register.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive
supply (DVDD) or VTHRESHOLD = DVDD/2 (±20%).
The internal digital circuitry of the AD9761 is capable of
operating over a digital supply range of 2.7 V to 5.5 V. As a
REV. C
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J0R-MZ-F2 | CONVERTER MOD DC/DC 7.5V 25W |
| SI5338K-A-GM | IC CLK GEN I2C BUS PROG 24QFN |
| D38999/20KF32PC | CONN RCPT 32POS WALL MNT W/PINS |
| MS3101A36-8S | CONN RCPT 47POS FREE HNG W/SCKT |
| M83723/84G1212N | CONN RCPT 12POS JAM NUT W/SCKT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9761ARSZRL | 功能描述:IC DAC 10BIT DUAL 40MSPS 28-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD9761-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9761 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9761 - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NS)) |
| AD9761-EBZ | 功能描述:BOARD EVAL FOR AD9761 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9762 | 制造商:AD 制造商全称:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table |
发布紧急采购，3分钟左右您将得到回复。