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参数资料
| 型号： | AD9761ARSZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT DUAL 40MSPS 28-SSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,500 |
| 设置时间： | 35ns |
| 位数： | 10 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 250mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极；4 电流，双极 |
| 采样率（每秒）： | 40M |
| 配用： | AD9761-EBZ-ND - BOARD EVAL FOR AD9761 |
AD9761
–10–
AD9761
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FUNCTIONAL DESCRIPTION
Figure 4 shows a simplified block diagram of the AD9761. The
AD9761 is a complete dual-channel, high speed, 10-bit CMOS
DAC capable of operating up to a 40 MHz clock rate. It has
been optimized for the transmit section of wideband communica-
tion systems employing I and Q modulation schemes. Excellent
matching characteristics between channels reduce the need for
any external calibration circuitry. Dual matching 2 interpola-
tion filters included in the I and Q data path simplify any post
band-limiting filter requirements. The AD9761 interfaces with a
single 10-bit digital input bus that supports interleaved I and Q
input data.
ACOM
REFLO
I
DAC
FSADJ
IOUTA
IOUTB
WRITE INPUT
SELECT INPUT
DCOM
DVDD
CLOCK
AD9761
2
LATCH
I
REFIO
REFERENCE
COMP1
COMP2
COMP3
BIAS
GENERATOR
QOUTA
QOUTB
2
LATCH
Q
MUX
CONTROL
AVDD
DAC DATA
INPUTS
(10 BITS)
SLEEP
Q
DAC
Figure 4. Dual DAC Functional Block Diagram
Referring to Figure 4, the AD9761 consists of an analog sec-
tion and a digital section.The analog section includes matched
I and Q 10-bit DACs, a 1.20 V band gap voltage reference, and
a reference control amplifier.The digital section includes two 2
interpolation filters, segment decoding logic, and some additional
digital input interface circuitry.The analog and digital sections of
the AD9761 have separate power supply inputs (i.e., AVDD and
DVDD) that can operate independently.The digital supply can
operate over a 2.7 V to 5.5 V range, allowing it to accommodate
TTL as well as 3.3 V and 5 V CMOS logic families.The analog
supply must be restricted from 3.0 V to 5.5 V to maintain opti-
mum performance.
Each DAC consists of a large PMOS current source array capable
of providing up to 10 mA of full-scale current, IOUTFS. Each array is
divided into 15 equal currents that make up the four most signifi-
cant bits (MSBs). The next four bits or middle bits consist of 15
equal current sources whose values are 1/16 of an MSB current
source. The remaining LSBs are binary weighted fractions of
the middle bits’ current sources. All of these current sources are
switched to one of two output nodes (i.e., IOUTA or IOUTB)
via PMOS differential current switches.
The full-scale output current, IOUTFS, of each DAC is regulated
from the same voltage reference and control amplifier, thus
ensuring excellent gain matching and drift characteristics
between DACs. IOUTFS can be set from 1 mA to 10 mA via an
external resistor, RSET. The external resistor in combination
with both the reference control amplifier and voltage reference,
VREFIO, sets the reference current, IREF, which is mirrored over
to the segmented current sources with the proper scaling factor.
IOUTFS is exactly 16 times the value of IREF.
The I and Q DACs are simultaneously updated on the rising
edge of CLOCK with digital data from their respective 2
digital interpolation filters. The 2 interpolation filters essen-
tially multiply the input data rate of each DAC by a factor of
2, relative to its original input data rate, while simultaneously
reducing the magnitude of the first image associated with the
DAC’s original input data rate. Since the AD9761 supports a
single 10-bit digital bus with interleaved I and Q input data, the
original I and Q input data rate before interpolation is one-half
the CLOCK rate. After interpolation, the data rate into each I
and Q DAC becomes equal to the CLOCK rate.
The benefits of an interpolation filter are illustrated in Figure 5,
which shows an example of the frequency and time domain rep-
resentation of a discrete time sine wave signal before and after
it is applied to a digital interpolation filter. Images of the sine
wave signal appear around multiples of the DAC’s input data
rate as predicted by the sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modified by the DAC’s sin(x)/(x) response. In many
band-limited applications, these images must be suppressed by
an analog filter following the DAC. The complexity of this ana-
FUNDAMENTAL
1
fCLOCK
FUNDAMENTAL DIGITAL
FILTER
SUPPRESSED
OLD
1ST IMAGE
NEW
1ST IMAGE
fCLOCK
1ST IMAGE
2
fCLOCK
fCLOCK
2
fCLOCK
DACs
SIN(X)
X
TIME DOMAIN
FREQUENCY DOMAIN
2 INTERPOLATION FILTER
INPUT DATA LATCH
DAC
fCLOCK
2
fCLOCK
2
fCLOCK
2
Figure 5.Time and Frequency Domain Example of Digital Interpolation Filter
REV. C
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9761-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9761 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9761 - Bulk 制造商:Analog Devices 功能描述:SEMICONDUCTOR ((NS)) |
| AD9761-EBZ | 功能描述:BOARD EVAL FOR AD9761 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9762 | 制造商:AD 制造商全称:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table |
| AD9762AR | 功能描述:IC DAC 12BIT 125MSPS 28-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
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