参数资料
| 型号： | AD9764ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/22页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 125MSPS 28-SOIC |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 27 |
| 系列： | TxDAC® |
| 设置时间： | 35ns |
| 位数： | 14 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 170mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 125M |
| 产品目录页面： | 785 (CN2011-ZH PDF) |
REV. B
AD9764
–12–
1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA.
Operation beyond the positive compliance range will induce
clipping of the output signal which severely degrades the
AD9764’s linearity and distortion performance.
For applications requiring the optimum dc linearity, IOUTA and/
or IOUTB should be maintained at a virtual ground via an I-V op
amp configuration. Maintaining IOUTA and/or IOUTB at a virtual
ground keeps the output impedance of the AD9764 fixed, signifi-
cantly reducing its effect on linearity. However, it does not
necessarily lead to the optimum distortion performance due to
limitations of the I-V op amp. Note that the INL/DNL speci-
fications for the AD9764 are measured in this manner using
IOUTA. In addition, these dc linearity specifications remain
virtually unaffected over the specified power supply range of
2.7 V to 5.5 V.
Operating the AD9764 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output configu-
ration reduces the signal dependency of its output impedance
thus enhancing distortion performance. Although the voltage
compliance range of IOUTA and IOUTB extends from –1.0 V to
+1.25 V, optimum distortion performance is achieved when the
maximum full-scale signal at IOUTA and IOUTB does not exceed
approximately 0.5 V. A properly selected transformer with a
grounded center-tap will allow the AD9764 to provide the re-
quired power and voltage levels to different loads while main-
taining reduced voltage swings at IOUTA and IOUTB. DC-coupled
applications requiring a differential or single-ended output con-
figuration should size RLOAD accordingly. Refer to Applying the
AD9764 section for examples of various output configurations.
The most significant improvement in the AD9764’s distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both IOUTA
and IOUTB can be substantially reduced by the common-mode
rejection of a transformer or differential amplifier. These
common-mode error sources include even-order distortion
products and noise. The enhancement in distortion performance
becomes more significant as the reconstructed waveform’s
frequency content increases and/or its amplitude decreases.
This is evident in Figure 14, which compares the differential
vs. single-ended performance of the AD9764 at 50 MSPS for
0.0 and –6.0 dBFS single tone waveforms over frequency.
The distortion and noise performance of the AD9764 is also
slightly dependent on the analog and digital supply as well as the
full-scale current setting, IOUTFS. Operating the analog supply at
5.0 V ensures maximum headroom for its internal PMOS current
sources and differential switches leading to improved distortion
performance as shown in Figure 8. Although IOUTFS can be set
between 2 mA and 20 mA, selecting an IOUTFS of 20 mA will
provide the best distortion and noise performance also shown in
Figure 8. The noise performance of the AD9764 is affected by
the digital supply (DVDD), output frequency, and increases
with increasing clock rate as shown in Figure 13. Operating the
AD9764 with low voltage logic levels between 3 V and 3.3 V
will slightly reduce the amount of on-chip digital noise.
In summary, the AD9764 achieves the optimum distortion and
noise performance under the following conditions:
(1) Differential Operation.
(2) Positive voltage swing at IOUTA and IOUTB limited to +0.5 V.
(3) IOUTFS set to 20 mA.
(4) Analog Supply (AVDD) set at 5.0 V.
(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-
priate logic levels.
Note that the ac performance of the AD9764 is characterized
under the above mentioned operating conditions.
DIGITAL INPUTS
The AD9764’s digital input consists of 14 data input pins and a
clock input pin. The 14-bit parallel data inputs follow standard
positive binary coding where DB13 is the most significant bit
(MSB), and DB0 is the least significant bit (LSB). IOUTA pro-
duces a full-scale output current when all data bits are at Logic
1. IOUTB produces a complementary output with the full-scale
current split between the two outputs as a function of the input
code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse-
width. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met,
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling
edge of a 50% duty cycle clock.
The digital inputs are CMOS-compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 (
±20%)
The internal digital circuitry of the AD9764 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure
proper compatibility with most TTL logic families. Figure 29
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9764 remains enabled if this input is left disconnected.
DVDD
DIGITAL
INPUT
Figure 29. Equivalent Digital Input
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| AD9764ARUZ | IC DAC 14BIT 125MSPS 28-TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9764ARZRL | 功能描述:IC DAC 14BIT 125MSPS 28SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD9764-EB | 制造商:Analog Devices 功能描述: |
| AD9764-EBZ | 功能描述:BOARD EVAL FOR AD9764 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9765 | 制造商:AD 制造商全称:Analog Devices 功能描述:Analog Devices: Data Converters: DAC 12-Bit, 10 ns to 100 ns Converters Selection Table |
| AD97651 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
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