参数资料
| 型号： | AD9778ABSVZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/56页 |
| 文件大小： | 0K |
| 描述： | DAC 14BIT 1.0GSPS 100-TQFP |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1,000 |
| 位数： | 14 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 300mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极；4 电流，双极 |
| 采样率（每秒）： | 1G |
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AD9776A/AD9778A/AD9779A
Rev. B | Page 25 of 56
THEORY OF OPERATION
The AD9776A/AD9778A/AD9779A have many features that
make them highly suited for wired and wireless communications
systems. The dual digital signal path and dual DAC structure
allow an easy interface with common quadrature modulators
when designing single sideband transmitters. The speed and
performance of the parts allow wider bandwidths and more
carriers to be synthesized than in previously available DACs.
The digital engine uses an innovative filter architecture that
combines the interpolation with a digital quadrature modulator.
This allows the parts to perform digital quadrature frequency
upconversions. The on-chip synchronization circuitry enables
multiple devices to be synchronized to each other, or to a
system clock.
DIFFERENCES BETWEEN AD9776/AD9778/
AD9779 AND AD9776A/AD9778A/AD9779A
REFCLK Maximum Frequency vs. Supply
With some restrictions on the DVDD18 and CVDD18 power
supplies, the AD9776A/AD9778A/AD9779A support a maxi-
mum sample rate of 1100 MHz. Table 2 lists the valid operating
frequencies vs. power supply voltage.
REFCLK Amplitude
With a differential sinusoidal clock applied to REFCLK, the
PLL on the AD9776/AD9778/AD9779 does not achieve optimal
noise performance unless the REFCLK differential amplitude is
increased to 2 V p-p. Note that if an LVPECL driver is used on the
AD9776/AD9778/AD9779, the PLL exhibits optimal performance
if the REFCLK amplitude is well within LVPECL specifications
(<1.6 V p-p differential). The design of the PLL on the AD9779A
has been improved so that even with a sinusoidal clock, the PLL
still achieves optimal amplitude if the swing is 1.6 V p-p.
PLL Lock Ranges
The individual lock ranges for the AD9776A/AD9778A/AD9779A
PLL are wider than those for the AD9776/AD9778/AD9779.
This means that the AD9776A/AD9778A/AD9779A PLL
remains in lock in a given range over a wider temperature range
than the AD9776/AD9778/AD9779. See Table 23 for PLL lock
ranges for the AD9776A/AD9778A/AD9779A.
PLL Optimal Settings
The optimal settings for the AD9776/AD9778/AD9779 differ
from the AD9776A/AD9778A/AD9779A. Refer to the PLL Bias
Settings section for complete details.
Input Data Delay Line, Manual and Automatic
Correction Modes
The AD9776A/AD9778A/AD9779A can be programmed to not
only sense when the timing margin on the input data falls below
a preset threshold but to also take action. The device can be
programmed to either set the IRQ (pin and register) or
automatically reoptimize the timing input data timing.
Input Data Timing
See Table 28 for timing specifications vs. temperature. The
input data timing specifications (setup and hold) are different
for the AD9776A/AD9778A/AD9779A than they are for the
AD9776/AD9778/AD9779.
DATACLK Delay Range
In the AD9776/AD9778/AD9779, the input data delay was
controlled by Register 0x04, Bits[7:4]. At 25°C, the delay was
stepped by approximately 180 ps/increment. In the AD9776A/
AD9778A/AD9779A, an extra bit has been added, which effectively
doubles the delay range. This bit is now located at Register 0x01,
Bit 1. The increment/step on the AD9776A/AD9778A/AD9779A
remains at ~180 ps.
Version Register
The version register (Register 0x1F) of the AD9776A/AD9778A/
AD9779A reads a value of 0x07. The version register of the
AD9776/AD9778/AD9779 reads a value of 0x03.
Table 10. Register Value Differences Between AD9776/AD9778/AD9779 and AD9776A/AD9778A/AD9779A
Part No.
PLL Loop Bandwidth,
Register 0x0A, Bits[4:0]
PLL Bias,
Register 0x09, Bits[2:0]
VCO Control Voltage,
Register 0x0A, Bits[7:5]
PLL VCO Drive,
Register 0x08, Bits[1:0]
AD9776/AD9778/AD9779
11111
111
010
00
AD9776A/AD9778A/AD9779A
01111
011
11
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| AD9778BSVZRL | IC DAC 14BIT DUAL 1GSPS 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9778A-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9778A RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9778A-EBZ | 制造商:Analog Devices 功能描述:Dual 12 /14 /16 Bit, 1 GSPS, Digital To Analog Converters Development Kit 制造商:Analog Devices 功能描述:DUAL 14B, 1.0 GSPS TXDAC - Bulk |
| AD9778BSVZ | 功能描述:IC DAC 14BIT DUAL 1GSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9778BSVZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters |
| AD9778BSVZRL | 功能描述:IC DAC 14BIT DUAL 1GSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
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