参数资料
| 型号： | AD9778BSVZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/56页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT DUAL 1GSPS 100TQFP |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1,000 |
| 位数： | 14 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 300mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极；4 电流，双极 |
| 采样率（每秒）： | 1G |
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AD9776/AD9778/AD9779
Rev. A | Page 35 of 56
INTERPOLATION FILTER MINIMUM AND
MAXIMUM BANDWIDTH SPECIFICATIONS
The AD977x uses a novel interpolation filter architecture that
allows DAC IF frequencies to be generated anywhere in the
spectrum. Figure 68 shows the traditional choice of DAC IF
output bandwidth placement. Note that there are no possible
filter modes in which the carrier can be placed near 0.5 × fDATA,
1.5 × fDATA, 2.5 × fDATA, and so on.
10
–80
–4
4
fOUT (× Input Data Rate),
ASSUMING 8
× INTERPOLATION
ATTE
NUATION
(dB)
0
–10
–20
–30
–40
–50
–60
–70
–3
–2
–1
0123
+f
DAC
/2
+f
DAC
/4
+f
DAC
/8
BAS
E
BAND
–f
DAC
/8
–f
DAC
/4
–f
DAC
/2
05361-065
Figure 68. Traditional Bandwidth Options for TxDAC Output IF
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the possi-
bility of a 3 × fDAC/8 modulation mode. With all of these filter
combinations, a carrier of given bandwidth can be placed
anywhere in the spectrum and fall into a possible pass band of
the interpolation filters. The possible bandwidths accessible
with the filter architecture are shown in Figure 69 and
Figure 70. Note that the shifted and nonshifted filter modes
are all accessible by programming the filter mode for the
particular interpolation rate.
10
–80
–4
4
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
AT
T
E
NUAT
IO
N
(
d
B)
0
–10
–20
–30
–40
–50
–60
–70
–3
–2
–1
0
1
2
3
–f
DA
C
/2
–3
×
f DAC
/8
–f
DA
C
/4
–f
DA
C
/8
B
A
SEB
A
N
D
+f
DAC
/8
+f
DAC
/4
+3
×
f DAC
/8
+f
DAC
/2
05
36
1-
0
66
Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture
10
–80
–4
4
fOUT (× Input Data Rate),
ASSUMING 8
× INTERPOLATION
ATTE
NUATION
(dB)
0
–10
–20
–30
–40
–50
–60
–70
–3
–2
–1
0
1
2
3
SHIFTED
–
3
×
f DAC
/8
SHIFTED
–f
DAC
/4
SHIFTED
–f
DAC
/8
SHIFTED
–
DC
SHIFTED
–
DC
SHIFTED
–f
DAC
/8
SHIFTED
–f
DAC
/4
SHIFTED
–
3
×
f DAC
/8
05361-067
Figure 70. Shifted Bandwidths Accessible with the Filter Architecture
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction
resulting from the combination of filter response and input
sample rate is often referred to as the synthesis bandwidth, since
this is the largest bandwidth that the DAC can synthesize.
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
width as a fraction of DAC output sample rate drops by a factor
of 2 for every doubling of interpolation rate. The minimum
bandwidth condition exists, for example, if a carrier is placed at
0.25 × fDATA. In this situation, if the nonshifted filter response is
enabled, the high end of the filter response cuts off at 0.4 × fDATA,
thus limiting the high end of the signal bandwidth. If the shifted
filter response is enabled instead, then the low end of the filter
response cuts off at 0.1 × fDATA, thus limiting the low end of the
signal bandwidth. The minimum bandwidth specification that
applies for a carrier at 0.25 × fDATA is therefore 0.3 × fDATA. The
minimum bandwidth behavior is repeated over the spectrum
for carriers placed at (±n ± 0.25) × fDATA, where n is any integer.
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
It is a PMOS input differential pair powered from
the 1.8 V supply, therefore, it is important to maintain the
specified 400 mV input common-mode voltage. Each input
pin can safely swing from 200 mV p-p to 1 V p-p about the
400 mV common-mode voltage. While these input levels are
not directly LVDS-compatible, REFCLK can be driven by an
offset ac-coupled LVDS signal, as shown in Figure 71.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9778BSVZRL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters |
| AD9778-EB | 制造商:Analog Devices 功能描述:EVAL BOARD 14-BIT DUAL INTERPOLATION DAC - Bulk |
| AD9778-EBZ | 制造商:Analog Devices 功能描述: |
| AD9779 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
| AD9779A | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters |
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