参数资料
| 型号： | AD9783BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BT 500MSPS LVDS 72LFCSP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 315mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 72-LFCSP-VQ（10x10） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，单极；4 电流，双极 |
| 采样率（每秒）： | 600M |
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AD9780/AD9781/AD9783
Data Sheet
Rev. B | Page 22 of 32
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 12.
Register
Address
Bit
Name
Function
SPI Control
0x00
7
SDIO_DIR
0, operate SPI in 4-wire mode. The SDIO pin operates as an input only pin.
1, operate SPI in 3-wire mode. The SDIO pin operates as a bidirectional data line.
6
LSBFIRST
0, MSB first per SPI standard.
1, LSB first per SPI standard.
Only change LSB/MSB order in single-byte instructions to avoid erratic behavior
due to bit order errors.
5
RESET
0, execute software reset of SPI and controllers, reload default register values
except Register 0x00.
1, set software reset, write 0 on the next (or any following) cycle to release the reset.
Data Control
0x02
7
DATA
0, DAC input data is twos complement binary format.
1, DAC input data is unsigned binary format.
4
INVDCO
1, inverts the data clock output. Used for adjusting timing of input data.
Power-Down
0x03
7
PD_DCO
1, power down data clock output driver circuit.
6
PD_INPT
1, power down input.
5
PD_AUX2
1, power down AUX2 DAC
4
PD_AUX1
1, power down AUX1 DAC.
3
PD_BIAS
1, power down voltage reference bias circuit.
2
PD_CLK
1, power down DAC clock input circuit.
1
PD_DAC2
1, power down DAC2.
0
PD_DAC1
1, power down DAC1.
Setup and Hold
0x04
7:4
SET[3:0]
4-bit value used to determine input data setup timing.
3:0
HLD[3:0]
4-bit value used to determine input data hold timing.
Timing Adjust
0x05
4:0
SAMP_DLY[4:0]
5-bit value used to optimally position input data relative to internal sampling clock.
Seek
0x06
2
LVDS low
One of the LVDS inputs is above the input voltage limits of the IEEE reduced link
specification.
1
LVDS high
One of the LVDS inputs is below the input voltage limits of the IEEE reduced link
specification.
0
SEEK
Indicator bit used with LVDS_SET and LVDS HLD to determine input data timing
margin.
Mix Mode
0x0A
3:2
DAC1MIX[1:0]
00, selects normal mode, DAC1.
01, selects return-to-zero mode, DAC1.
10, selects return-to-zero mode, DAC1.
11, selects mix mode, DAC1.
1:0
DAC2MIX[1:0]
00, selects normal mode, DAC2.
01, selects return-to-zero mode, DAC2.
10, selects return-to-zero mode, DAC2.
11, selects mix mode, DAC2.
DAC1 FSC
0x0B
7:0
DAC1FSC[9:0]
DAC1 full-scale 10-bit adjustment word.
0x0C
1:0
0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
0x200, sets DAC full-scale output current to the nominal value of 20.0 mA.
0x000, sets DAC full-scale output current to the minimum value of 8.66 mA.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9783BCPZRL | 功能描述:IC DAC 16BT 500MSPS LVDS 72LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD9783-DPG2-EBZ | 功能描述:BOARD EVAL FOR AD9783 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9783-DUAL-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, 500 MSPS LVDS DAC - Boxed Product (Development Kits) |
| AD9783-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, 600 MSPS LVDS DAC - Bulk |
| AD9784 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 200 MSPS/500 MSPS TxDAC+ with 2×/4×/8× Interpolation and Signal Processing |
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