参数资料
| 型号： | AD9814JR |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/15页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC 14BIT 28-SOIC |
| 标准包装： | 27 |
| 类型： | CCD 信号处理器，14 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 电流 - 电源： | 80mA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
REV. 0
–2–
AD9814–SPECIFICATIONS
ANALOG SPECIFICATIONS
J-Grade
K-Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Units
CONVERSION RATE
3-Channel Mode with CDS
6
10
6
10
MSPS
1-Channel Mode with CDS
6
7
6
7
MSPS
ACCURACY (Entire Signal Path)
ADC Resolution
14
Bits
Integral Nonlinearity
1 (INL)
+2.5/–6.0
±11.0
LSB
INL @ 10 MHz
+4.0/–7.0
LSB
Differential Nonlinearity (DNL)
+0.6/–0.5
±1.0
LSB
DNL @ 10 MHz
+0.8/–0.6
LSB
No Missing Codes Guaranteed
13
14
Bits
Offset Error
–12
±104
mV
Gain Error
2
2.2
±5.3
% FSR
ANALOG INPUTS
Input Signal Range
3
4.0
V p-p
Allowable Reset Transient
3
1.0
V
Input Limits
4
AVSS – 0.3
AVDD + 0.3
AVSS – 0.3
AVDD + 0.3
V
Input Capacitance
10
pF
Input Bias Current
10
nA
AMPLIFIERS
PGA Gain at Minimum
1
V/V
PGA Gain at Maximum
5.8
V/V
PGA Resolution
64
Steps
PGA Monotonicity
Guaranteed
Programmable Offset at Minimum
–300
mV
Programmable Offset at Maximum
+300
mV
Programmable Offset Resolution
512
Steps
Programmable Offset Monotonicity
Guaranteed
NOISE AND CROSSTALK
Input Referred Noise @ PGA Min
130
V rms
Total Output Noise @ PGA Min
0.55
LSB rms
Input Referred Noise @ PGA Max
84
V rms
Total Output Noise @ PGA Max
2.0
LSB rms
Channel-Channel Crosstalk
<1
LSB
POWER SUPPLY REJECTION
AVDD = +5 V
± 0.25 V
0.07
0.3
% FSR
Differential VREF (@ +25
°C)
CAPT-CAPB (4 V Input Range)
2.0
1.9
2.0
2.1
V
CAPT-CAPB (2 V Input Range)
1.0
0.94
1.0
1.06
V
TEMPERATURE RANGE
Operating
0
+70
0
+70
°C
Storage
–65
+150
–65
+150
°C
POWER SUPPLIES
AVDD
+4.75
+5.0
+5.25
+4.75
+5.0
+5.25
V
DRVDD
+3.0
+5.0
+5.25
+3.0
+5.0
+5.25
V
Total Operating Current
AVDD
64
80
mA
DRVDD
1.8
10
mA
Power-Down Mode Current
150
A
Power Dissipation
330
450
mW
Power Dissipation @ 10 MHz
355
mW
Power Dissipation (1-Channel Mode)
220
265
mW
(TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, fADCCLK = 6 MHz, fCDSCLK1 = fCDSCLK2 =
2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.)
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