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| 型号： | AD9830ASTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC DDS 10BIT 50MHZ CMOS 48-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 50MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
| 配用： | EVAL-AD9830EBZ-ND - BOARD EVALUATION AD9830 |
AD9830
–5–
PIN DESCRIPTION
Mnemonic
Function
POWER SUPPLY
AVDD
Positive power supply for the analog section. A 0.1
F capacitor should be connected between AVDD and
AGND. AVDD has a value of +5 V
± 5%.
AGND
Analog Ground.
DVDD
Positive power supply for the digital section. A 0.1
F decoupling capacitor should be connected between DVDD
and DGND. DVDD has a value of +5 V
± 5%.
DGND
Digital Ground.
ANALOG SIGNAL AND REFERENCE
IOUT, IOUT
Current Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND.
FS ADJUST
Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the mag-
nitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
IOUTFULL-SCALE = 16 VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 1 k
typical
REFIN
Voltage Reference Input. The AD9830 can be used with either the on-board reference, which is available from pin
REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9830 ac-
cepts a reference of 1.21 V nominal.
REFOUT
Voltage Reference Output. The AD9830 has an on-board reference of value 1.21 V nominal. The reference is
made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGITAL INTERFACE AND CONTROL
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase ac-
cumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when an MCLK rising edge occurs, there is an uncertainty
of one MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a
change on FSELECT should not coincide with an MCLK rising edge.
WR
Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9830. The data is loaded
into the AD9830 on the rising edge of the WR pulse. This data is then loaded into the destination register on the
MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR ris-
ing edge should occur before an MCLK rising edge. The data will then be transferred into the destination register
on the MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the desti-
nation register will be loaded on the next MCLK rising edge.
D0–D15
Data Bus, Digital Inputs for destination registers.
A0–A2
Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1
Phase Select Input. The AD9830 has four phase registers. These registers can be used to alter the value being in-
put to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the inputs
PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, the AD9830 samples the
PSEL0 and PSEL1 inputs on the MCLK rising edge. Therefore, these inputs should be in steady state at the
MCLK rising edge or, there is an uncertainty of one MCLK cycle as to when control is transferred to the selected
phase register.
SLEEP
Low Power Control, active low digital input. SLEEP puts the AD9830 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. The AD9830 is re-enabled by taking
SLEEP
high.
RESET
Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog
output of midscale.
REV. B
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相关代理商/技术参数 |
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| AD9830ASTZ-REEL | 功能描述:IC DDS 10BIT 50MHZ CMOS 48TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9831 | 制造商:AD 制造商全称:Analog Devices 功能描述:CMOS Complete DDS |
| AD9831AST | 制造商:Rochester Electronics LLC 功能描述:25 MHZ +5V/+3V, 10-BIT DDS DAC I.C. - Bulk 制造商:Analog Devices 功能描述:10BIT DAC DDS 25 MHZ +5V/+3V 9831 |
| AD9831AST-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 25MHz 1-DAC 10-Bit Parallel 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:25 MHZ +5V/+3V, 10-BIT DDS DAC I.C. - Tape and Reel |
| AD9831ASTZ | 功能描述:IC DDS 10BIT 25MHZ CMOS 48-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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