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参数资料
| 型号： | AD9834BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/32页 |
| 文件大小： | 0K |
| 描述： | IC DDS 10BIT 50MHZ LP 20TSSOP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | Amplitude Control Circuit for AD9834 Waveform Generator (CN0156) |
| 标准包装： | 1,000 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 50MHz |
| 调节字宽（位）： | 28 b |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
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AD9834
Data Sheet
Bit
Name
Description
DB5
OPBITEN
The function of this bit is to control whether there is an output at the SIGN BIT OUT pin. This bit should remain at 0 if the
user is not using the SIGN BIT OUT pin.
OPBITEN = 1 enables the SIGN BIT OUT pin.
OPBITEN = 0, the SIGN BIT OUT output buffer is put into a high impedance state, therefore no output is available at the
SIGN BIT OUT pin.
DB4
SIGN/PIB
The function of this bit is to control what is output at the SIGN BIT OUT pin.
SIGN/PIB = 1, the on-board comparator is connected to SIGN BIT OUT. After filtering the sinusoidal output from the
DAC, the waveform can be applied to the comparator to generate a square waveform. Refer to Table 17.
SIGN/PIB = 0, the MSB (or MSB/2) of the DAC data is connected to the SIGN BIT OUT pin. Bit DIV2 controls whether it is
the MSB or MSB/2 that is output.
DB3
DIV2
DIV2 is used in association with SIGN/PIB and OPBITEN. Refer to Table 17.
DIV2 = 1, the digital output is passed directly to the SIGN BIT OUT pin.
DIV2 = 0, the digital output/2 is passed directly to the SIGN BIT OUT pin.
DB2
Reserved
This bit must always be set to 0.
DB1
MODE
The function of this bit is to control what is output at the IOUT pin/IOUTB pin. This bit should be set to 0 if the Control
Bit OPBITEN = 1.
MODE = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC.
MODE = 0, the SIN ROM is used to convert the phase information into amplitude information, resulting in a sinusoidal
signal at the output. See Table 18.
DB0
Reserved
This bit must always be set to 0.
FREQUENCY AND PHASE REGISTERS
The AD9834 contains two frequency registers and two phase
registers. These are described in Table 7.
Table 7. Frequency/Phase Registers
Register
Size
Description
FREQ0
28 bits
Frequency Register 0. When either the
FSEL bit or FSELECT pin = 0, this register
defines the output frequency as a fraction
of the MCLK frequency.
FREQ1
28 bits
Frequency Register 1. When either the
FSEL bit or FSELECT pin = 1, this register
defines the output frequency as a fraction
of the MCLK frequency.
PHASE0
12 bits
Phase Offset Register 0. When either the
PSEL bit or PSELECT pin = 0, the contents
of this register are added to the output of
the phase accumulator.
PHASE1
12 bits
Phase Offset Register 1. When either the
PSEL bit or PSELECT pin = 1, the contents
of this register are added to the output of
the phase accumulator.
The analog output from the AD9834 is
fMCLK/228 × FREQREG
where FREQREG is the value loaded into the selected frequency
register. This signal is phase shifted by
2π/4096 × PHASEREG
where PHASEREG is the value contained in the selected phase
register. Consideration must be given to the relationship of the
selected output frequency and the reference clock frequency to
avoid unwanted output anomalies.
Access to the frequency and phase registers is controlled by
both the FSELECT and PSELECT pins, and the FSEL and PSEL
control bits. If the Control Bit PIN/SW = 1, the pins control the
function; whereas, if PIN/SW = 0, the bits control the function.
This is outlined in Table 8 and Table 9. If the FSEL and PSEL
bits are used, the pins should be held at CMOS logic high or
low. Control of the frequency/phase registers is interchangeable
from the pins to the bits.
Table 8. Selecting a Frequency Register
FSELECT
FSEL
PIN/SW
Selected Register
0
X
1
FREQ0 REG
1
X
1
FREQ1 REG
X
0
FREQ0 REG
X
1
0
FREQ1 REG
Table 9. Selecting a Phase Register
PSELECT
PSEL
PIN/SW
Selected Register
0
X
1
PHASE0 REG
1
X
1
PHASE1 REG
X
0
PHASE0 REG
X
1
0
PHASE1 REG
The FSELECT pin and PSELECT pin are sampled on the internal
falling edge of MCLK. It is recommended that the data on these
pins does not change within a time window of the falling edge of
MCLK (see Figure 4 for timing). If FSELECT or PSELECT changes
value when a falling edge occurs, there is an uncertainty of one
MCLK cycle because it pertains to when control is transferred
to the other frequency/phase register.
The flow charts in Figure 32 and Figure 33 show the routine
for selecting and writing to the frequency and phase registers
of the AD9834.
Rev. D | Page 20 of 32
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