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| 型号： | AD9851BRSZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESR DDS/DAC 28SSOP TR |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1,500 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 180MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 2.7 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
AD9851
–15–
Results of Reset, Figure 14
– Phase accumulator zeroed such that the output = 0 Hz (dc)
– Phase offset register set to 0 such that DAC IOUT = full-scale
output and IOUTB = zero mA output
– Internal programming address pointer reset to W0
– Power-down bit reset to 0 (power-down disabled)
– 40-bit data input register is NOT cleared
– 6 reference clock multiplier is disabled
– Parallel programming mode selected by default
XXXXX10X
FQ UD
W CLK
SYSCLK
DAC
STROBE
DATA (W0)
INTERNAL CLOCKS
DISABLED
Figure 15. Parallel Load Power-Down Sequence/
Internal Operation
XXXXX00X
FQ UD
W CLK
DATA (W0)
INTERNAL CLOCKS
ENABLED
SYSCLK
Figure 16. Parallel Load Power-Up Sequence (to
Recover from Power-Down)/Internal Operation
Entry to the serial mode, see Figure 17, is via the parallel mode,
which is selected by default after a RESET is asserted. One needs
only to program the first eight bits (word W0) with the sequence
xxxxx011 as shown in Figure 17 to change from parallel to serial
mode.The W0 programming word may be sent over the 8-bit
data bus or hardwired as shown in Figure 18. After serial mode
is achieved, the user must follow the programming sequence of
Figure 19.
XXXXX011
FQ UD
W CLK
DATA (W0)
ENABLE
SERIAL MODE
Figure 17. Serial Load Enable Sequence
Note: After serial mode is invoked, it is best to immediately write
a valid 40-bit serial word (see Figure 19), even if it is all zeros,
followed by a FQ_UD rising edge to flush the residual data left in
the DDS core. A valid 40-bit serial word is any word where W33
is Logic 0.
28
27
26
25
1
2
3
4
AD9851
D3
D2
D1
D0
D4
D5
D6
D7
10k
+V
SUPPLY
Figure 18. Hardwired xxxxx011 Configuration for
Serial Load Enable Word W0 in Figure 17
SYSCLK
RESET
AOUT
tRH
tRL
COS (0)
SYMBOL
DEFINITION
MIN SPEC
tRH
CLK DELAY AFTER RESET RISING EDGE 3.5ns*
tRL
RESET FALLING EDGE AFTER CLK
3.5ns*
tRR
RECOVERY FROM RESET
2 SYSCLK CYCLES
tRS
MINIMUM RESET WIDTH
5 SYSCLK CYCLES
tOL
RESET OUTPUT LATENCY
13 SYSCLK CYCLES
*SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED
tRR
NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME
NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT
HAVE TO BE SYNCHRONOUS TO THE SYSCLK IF THE MINIMAL TIME IS NOT REQUIRED.
tRS
tOL
Figure 14. Master ResetTiming Sequence
Note:The timing diagram above shows the minimal amount of reset time needed before writing to the device. However, the master reset does not have to be synchronous to
the SYSCLK if the minimal time is not required.
REV. D
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