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参数资料
| 型号： | AD9888KSZ-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/36页 |
| 文件大小： | 0K |
| 描述： | IC FLAT PANEL INTERFACE 128-MQFP |
| 标准包装： | 66 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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Data Sheet
AD9888
Rev. C | Page 27 of 36
Address 0x0F[4]—Coast Input Polarity Override
This bit is used to override the internal circuitry that determines
the polarity of the COAST signal going into the PLL.
Table 22. Coast Input Polarity Override Settings
Coast Input Polarity
Override Setting
Function
0 (default)
Coast polarity is determined by chip.
1
Coast polarity is determined by user.
Address 0x0F[3]—Coast Input Polarity
This bit indicates the polarity of the COAST signal that is
applied to the PLL coast input.
Table 23. Coast Input Polarity Settings
Coast Input Polarity
Setting
Function
0
Active low
1 (default)
Active high
Active low means that the clock generator ignores HSYNC
inputs when COAST is low and continues operating at the same
nominal frequency until COAST goes high.
Active high means that the clock generator ignores HSYNC
inputs when COAST is high and continues operating at the
same nominal frequency until COAST goes low.
This function needs to be used along with the coast polarity
override bit (Bit 4).
Address 0x0F[2]—Seek Mode Override
This bit is used to either enable or disable the low power mode.
The low power mode (seek mode) occurs when there are no
signals on any of the sync inputs.
Table 24. Seek Mode Override Settings
Seek Mode Override
Setting
Function
0
Disable seek mode
1 (default)
Enable seek mode
Address 0x0F[1]—PWRDN
This bit is used to put the chip into power-down mode. In this
mode, the power dissipation of the chip is reduced to a fraction
of the typical power (see the specifications in Table 1 for exact
power dissipation). When the chip is in power-down mode, the
HSOUT, VSOUT, DATACK, DATACK, and all 48 of the data
outputs are put into a high impedance state. Note that the
SOGOUT output is not put into high impedance. Circuit blocks
that continue to be active during power-down mode include the
voltage references, sync processing, sync detection, and the serial
register. These blocks facilitate a fast startup from power-down.
Table 25. PWRDN Settings
PWRDN Setting
Function
0
Power-down
1 (default)
Normal operation
Address 0x10[7:3]—Sync-on-Green Slicer Threshold
These bits allow the comparator threshold of the sync-on-green
slicer to be adjusted. The threshold can be adjusted in steps of
10 mV, with a minimum setting of 10 mV and a maximum
setting of 330 mV.
The default setting is 01111, which corresponds to a threshold
value of 0.16 V.
Address 0x10[2]—Red Clamp Select
This bit determines whether the red channel is clamped to
ground or to midscale. For RGB video, all three channels are
referenced to ground. For YCbCr (or YUV), the Y channel is
referenced to ground, but the CbCr channels are referenced to
midscale. Clamping to midscale clamps to Pin 9.
Table 26. Red Clamp Select Settings
Red Clamp Select Setting
Function
0 (default)
Clamp to ground
1
Clamp to midscale (Pin 9)
Address 0x10[1]—Blue Clamp Select
This bit determines whether the blue channel is clamped to
ground or to midscale. Clamping to midscale clamps to Pin 24.
Table 27. Blue Clamp Select Settings
Blue Clamp Select Setting
Function
0 (default)
Clamp to ground
1
Clamp to midscale (Pin 24)
Address 0x11[7:0]—Sync Separator Threshold
These bits are used to set the responsiveness of the sync separator.
The bits set how many internal 5 MHz clock periods the sync
separator must count before toggling high or low. This functions
like a low-pass filter to ignore HSYNC pulses to extract the VSYNC
signal. The bits should be set to a number greater than the maxi-
mum HSYNC pulse width. The sync separator threshold uses an
internal dedicated clock with a frequency of approximately 5 MHz.
The default for this register is 0x20.
Address 0x12[7:0]—Pre-COAST
These bits allow the COAST signal to be applied prior to the
VSYNC signal. This is necessary in cases where preequali
zation pulses are present. The step size for this control is one
HSYNC period.
The default is 0.
Address 0x13[7:0]—Post-COAST
This register allows the COAST signal to be applied after the
VSYNC signal. This is necessary in cases where postequali-
zation pulses are present. The step size for this control is one
HSYNC period.
The default setting for each of these bits is 0.
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