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参数资料
| 型号： | AD9888KSZ-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | IC FLAT PANEL INTERFACE 128-MQFP |
| 标准包装： | 66 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 2 线串口 |
| 电源电压： | 3 V ~ 3.6 V |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-MQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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Data Sheet
AD9888
Rev. C | Page 13 of 36
ground, black is at 300 mV, and white is at approximately 1.0 V.
Some common RGB line amplifier boxes use emitter-follower
buffers to split signals and increase drive capability. This
introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9888.
The key to clamping is to identify a time when the graphics system
is known to be producing black. An offset is then introduced,
which results in the ADCs producing a black output (Code 0x00)
when the known black input is present. The offset then remains
in place when other signal levels are processed, and the entire
signal is shifted to eliminate offset errors.
In most graphics systems, black is transmitted between active video
lines. In CRT displays, when the electron beam has completed
writing a horizontal line on the right side of the screen, the
beam is deflected quickly to the left side of the screen (called
horizontal retrace), and a black signal is provided to prevent the
beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT to begin a
retrace. It is important to avoid clamping on the tip of HSYNC.
Fortunately, there is almost always a period following HSYNC,
called the back porch, when a good black reference is provided.
This is the time when clamping should be performed.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time with external clamp
selected (clamp input signal source bit = 1). The polarity of this
signal is set by the clamp polarity bit (Register 0x0F, Bit 6).
A simpler method of clamp timing employs the AD9888
internal clamp timing generator. The clamp placement register
(Register 0x05) is programmed with the number of pixel times
that should pass after the trailing edge of HSYNC before clamping
begins. A second register (clamp duration, Register 0x06) sets
the duration of the clamp. Both registers are 8-bit values,
providing considerable flexibility in clamp generation. The
clamp timing is referenced to the trailing edge of HSYNC,
because, though HSYNC duration can vary widely, the back
porch (black reference) always follows HSYNC. A good starting
point for establishing clamping is to set the clamp placement to
Value 0x08 (providing eight pixel periods for the graphics signal
to stabilize after sync) and set the clamp duration to Value 0x14
(giving the clamp 20 pixel periods to reestablish the black
reference).
Clamping is accomplished by placing an appropriate charge on the
external input coupling capacitor. The value of this capacitor affects
the performance of the clamp. If it is too small, there is a significant
amplitude change during a horizontal line time (between clamping
intervals). If the capacitor is too large, it takes an excessively long
time for the clamp to recover from a large change in incoming
signal offset. The recommended value (47 nF) results in recovering
from a step error of 100 mV to within 1/2 LSB in 10 lines with a
clamp duration of 20 pixel periods on a 60 Hz SXGA signal.
YUV Clamping
YUV graphics signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the video signal rather than at the bottom. For
these signals, it might be necessary to clamp to the midscale of
the ADC range (Value 0x80) rather than to the bottom of the
ADC range (Value 0x00).
Clamping to midscale rather than to ground can be accomplished
by setting the clamp select bits in Register 0x10. The red and
blue channels each have their own selection bit so that they can
be clamped to either midscale or ground independently. The
clamp controls are located in Register 0x10, Bit 1 and Bit 2. The
midscale reference voltage that each ADC clamps to is provided
independently on the RMIDSCV and BMIDSCV pins. These
two pins should be bypassed to ground using a 0.1 μF capacitor,
even if midscale clamping is not required.
GAIN AND OFFSET CONTROL
The AD9888 can accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The full-scale range is set
in three 8-bit registers (red gain, green gain, and blue gain;
Register 0x08, Register 0x09, and Register 0x0A, respectively).
Increasing the gain setting results in an image with less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (red offset,
green offset, blue offset; Register 0x0B, Register 0x0C, and
Register 0x0D, respectively) provide independent settings for
each channel.
The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full-scale range. Therefore, if the
input range is doubled (from 0.5 V to 1.0 V), the offset step size
is also doubled (from 2 mV per step to 4 mV per step).
Figure 5 illustrates the interaction of gain and offset controls. The
magnitude of an LSB in offset adjustment is proportional to the
full-scale range; therefore, changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same
amount as the zero-scale level.
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