AD9911/PCBZ (Analog) PDF资料下载 Datasheet(26/44 页)

您好，
买卖IC网欢迎您。
请登录
免费注册

您现在的位置：买卖IC网 > PDF目录16458 > AD9911/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9911 PDF资料下载

参数资料

型号：	AD9911/PCBZ
厂商：	Analog Devices Inc
文件页数：	26/44页
文件大小：	0K
描述：	BOARD EVAL FOR AD9911
产品培训模块：	Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
设计资源：	AD9911 Eval Brd Schematics AD9911 Eval Brd BOM AD9911 Eval Brd Gerber Files
标准包装：	1
系列：	AgileRF™
主要目的：	计时，直接数字合成（DDS）
已用 IC / 零件：	AD9911
已供物品：	板
相关产品：	AD9911BCPZ-REEL7-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP AD9911BCPZ-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP

AD9911

Rev. 0 | Page 32 of 44

Single-Bit Serial (2- and 3-Wire) Modes

The single-bit serial mode interface allows read/write access to

all registers that configure the AD9911. MSB-first or LSB-first

transfer formats and the SYNC_I/O function are supported.

In 2-wire mode, the SDIO_0 pin is the single serial data I/O pin.

In 3-wire mode, the SDIO_0 pin is the serial data input pin and

the SDIO_2 pin is the output. For both modes, the SDIO_3 pin

is configured as an input and operates as the SYNC_I/O pin.

The SDIO_1 pin is unused.

2-Bit Mode

The SPI port operation in 2-bit mode is identical to the SPI port

operation in single bit mode, except that two bits of data are

registered on each rising edge of SCLK, cutting in half the

number of cycles required to program the device. The SDIO_0

pin contains the even numbered data bits using the notation D

<7:0> while the SDIO_1 pin contains the odd numbered data

bits regardless of whether in MSB- or LSB-first format (see

Figure 47).

4-Bit Mode

The SPI port in 4-bit mode is identical to the SPI port in single

bit mode, except that four bits of data are registered on each

rising edge of SCLK.

This reduces by 75% the number of cycles required to program

the device. Note that when reprogramming the device for 4-bit

mode, it is important to keep the SDIO_3 pin at Logic 0 until

the device is programmed out of the single bit serial mode.

Failure to do so can result in the I/O port controller being out of

sequence.

Figure 50 through Figure 52 are write timing diagrams for the

I/O modes available. Both MSB and LSB-first modes are shown.

LSB-first bits are shown in parenthesis. The clock stall low/high

feature shown is not required, but rather is used to show that

data (SDIO) must have the proper setup time relative to the

rising edge of SCLK.

Figure 53 through Figure 56 are read timing diagrams for each

I/O mode available. Both MSB and LSB-first modes are shown.

LSB-first bits are shown in parenthesis. The clock stall low/high

feature shown is not required. It is used to show that data

(SDIO) must have the proper set-up time relative to the rising

edge of SCLK for the instruction byte and the read data that

follows the falling edge of SCLK.

SCLK

SDIO_0

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

(I0)

(I1)

(I2)

(I3)

(I4)

(I5)

(I6)

(I7)

(D0)

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

Figure 50. Single-Bit Serial Mode Write Timing—Clock Stall Low