参数资料
型号: AD9951YSVZ
厂商: Analog Devices Inc
文件页数: 10/28页
文件大小: 0K
描述: IC DDS DAC 14BIT 1.8V 48-TQFP
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
标准包装: 1
分辨率(位): 14 b
主 fclk: 400MHz
调节字宽(位): 32 b
电源电压: 1.71 V ~ 1.96 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP 裸露焊盘(7x7)
包装: 托盘
产品目录页面: 552 (CN2011-ZH PDF)
AD9951
Rev. A | Page 18 of 28
AUTO Shaped On-Off Keying Mode Operation
The auto shaped on-off keying mode is active when CFR1<25>
and CFR1<24> are set. When auto shaped on-off keying mode
is enabled, a single scale factor is internally generated and
applied to the multiplier input for scaling the output of the DDS
core block (see Figure 18). The scale factor is the output of a
14-bit counter that increments/decrements at a rate determined
by the contents of the 8-bit output ramp rate register. The scale
factor increases if the OSK pin is high and decreases if the OSK
pin is low. The scale factor is an unsigned value such that all 0s
multiply the DDS core output by 0 (decimal) and 0x3FFF
multiplies the DDS core output by 16383 (decimal).
For those users who use the full amplitude (14-bits) but need
fast ramp rates, the internally generated scale factor step size
is controlled via the ASF<15:14> bits. Table 6 describes the
increment/decrement step size of the internally generated scale
factor per the ASF<15:14> bits.
A special feature of this mode is that the maximum output
amplitude allowed is limited by the contents of the amplitude
scale factor register. This allows the user to ramp to a value less
than full scale.
Table 6. Auto-Scale Factor Internal Step Size
ASF<15:14> (Binary)
Increment/Decrement Size
00
1
01
2
10
4
11
8
OSK Ramp Rate Timer
The OSK ramp rate timer is a loadable down counter, which
generates the clock signal to the 14-bit counter that generates
the internal scale factor. The ramp rate timer is loaded with the
value of the ASFR every time the counter reaches 1 (decimal).
This load and countdown operation continues for as long as the
timer is enabled, unless the timer is forced to load before
reaching a count of 1.
If the load OSK timer bit (CFR1<26>) is set, the ramp rate
timer is loaded upon an I/O UPDATE or upon reaching a value
of 1. The ramp timer can be loaded before reaching a count of 1
by three methods.
Method one is by changing the OSK input pin. When the OSK
input pin changes state, the ASFR value is loaded into the ramp
rate timer, which then proceeds to count down as normal.
The second method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is if the load OSK timer bit
(CFR1<26>) is set and an I/O UPDATE is issued.
The last method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is when going from the
inactive auto shaped on-off keying mode to the active auto
shaped on-off keying mode; that is, when the sweep enable bit is
being set.
03
35
9-
0
05
OSK PIN
LOAD OSK TIMER
CFR1<26>
SYNC_CLK
AUTO DESK
ENABLE
CFR1<24>
TO DAC
AUTO SCALE
FACTOR GENERATOR
RAMP RATE TIMER
CLOCK
DDS CORE
OSK ENABLE
CFR<25>
AMPLITUDE SCALE
FACTOR REGISTER
(ASF)
0
1
01
HOLD
INC/DEC ENABLE
OUT
COS(X)
AMPLITUDE RAMP
RATE REGISTER
(ASF)
UP/DN
DATA
LOAD
EN
Figure 18. On-Off Shaped Keying, Block Diagram
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