参数资料
| 型号： | AD9951YSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
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AD9951
Rev. A | Page 19 of 28
External Shaped On-Off Keying Mode Operation
The external shaped on-off keying mode is enabled by writing
CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0.
When configured for external shaped on-off keying, the
content of the ASFR becomes the scale factor for the data path.
The scale factors are synchronized to SYNC_CLK via the
I/O UPDATE functionality.
Synchronization; Register Updates (I/O UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9951 is synchronous to the SYNC_CLK signal
(supplied externally to the user on the SYNC_CLK pin). The
I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-4 frequency divider to
produce the SYNC_CLK signal. The SYNC_CLK signal is
provided to the user on the SYNC_CLK pin. This enables
synchronization of external hardware with the device’s internal
clocks. This is accomplished by forcing any external hardware
to obtain its timing from SYNC_CLK. The I/O UPDATE signal
coupled with SYNC_CLK is used to transfer internal buffer
contents into the control registers of the device. The combina-
tion of the SYNC_CLK and I/O UPDATE pins provides the
user with constant latency relative to SYSCLK, and also ensures
phase continuity of the analog output signal when a new tuning
word or phase offset value is asserted. Figure 19 demonstrates
an I/O UPDATE timing cycle and synchronization.
Notes to synchronization logic:
1.
The I/O UPDATE signal is edge detected to generate a
single rising edge clock signal that drives the register bank
flops. The I/O UPDATE signal has no constraints on duty
cycle. The minimum low time on I/O UPDATE is one
SYNC_CLK clock cycle.
2.
The I/O UPDATE pin is set up and held around the rising
edge of SYNC_CLK and has zero hold time and 4 ns setup
time.
03
35
9-
0
06
SYSCLK
SDI
SYNC_CLK
DISABLE
10
0
SCLK
TO CORE LOGIC
CS
OSK
D
Q
D
Q
I/O UPDATE
D
Q
÷ 4
SYNC_CLK
GATING
EDGE
DETECTION
LOGIC
REGISTER
MEMORY
I/O BUFFER
LATCHES
Figure 19. I/O Synchronization Block Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| AD9952YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
| AD9953YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
| AD9954YSVZ-REEL7 | IC DDS DAC 14BIT 1.8V 48TQFP |
| AD9956YCPZ-REEL7 | IC SYNTHESIZER 1.8V 48LFCSP |
| AD9957BSVZ-REEL | IC DDS 1GSPS 14BIT IQ 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9951YSVZ-REEL7 | 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48TQFP EP TAPE AND REEL - Tape and Reel |
| AD9952 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9952/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For Digital Synthesizer 制造商:Analog Devices 功能描述:400 MSPS 14BIT CMOS DIRECT DGTL SYNTHESIZER - Bulk 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9952YSV | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9952 TQFP48 |
| AD9952YSV-REEL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
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