- 您现在的位置：买卖IC网 > PDF目录10979 > AD9956YCPZ (Analog Devices Inc)IC SYNTHESIZER 1.8V 48LFCSP PDF资料下载
参数资料
| 型号： | AD9956YCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER 1.8V 48LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 3GHz |
| 调节字宽（位）： | 48 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9956-VCO/PCBZ-ND - BOARD EVAL 14BIT 1.8V 48LFCSP AD9956/PCBZ-ND - BOARD EVAL FOR AD9956 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页
AD9956
Rev. A | Page 18 of 32
GENERAL DESCRIPTION
DDS CORE
The DDS can create digital phase relationships by clocking a
48-bit accumulator. The incremental value loaded into the
accumulator, known as the frequency tuning word, controls the
overflow rate of the accumulator. Similar to a sine wave com-
pleting a 2π radian revolution, the overflow of the accumulator
is cyclical in nature and generates a base frequency according to
the following equation.
48
2
)
( s
o
f
FTW
f
×
=
}
2
0
{
47
≤
≤ FTW
The instantaneous phase of the sine wave is, therefore, the out-
put of the phase accumulator block. This signal can be phase-
offset by programming an additive digital phase added to each
and every phase sample coming out of the accumulator.
These instantaneous phase values are then piped through a
phase-to-amplitude conversion (sometimes called an angle-
to-amplitude conversion or AAC) block. This algorithm follows
a COS(x) relationship where x is the phase coming out of the
phase offset block, normalized to 2π.
Finally, the amplitude words are piped to a 14-bit DAC. Because
the DAC is a sampled data system, the output is a reconstructed
sine wave that needs to be filtered to take high frequency
images out of the spectrum. The DAC is a current-steering
DAC that is AVDD referenced. To get a measurable voltage
output, the DAC outputs must terminate through a load resistor
to AVDD, typically 50 . At positive full scale, IOUT sinks no
current and the voltage drop across the load resistor is zero.
However, the IOUT output sinks the DAC’s programmed full-
scale output current, causing the maximum output voltage to
drop across the load resistor. At negative full-scale, the situation
is reversed and IOUT sinks the full-scale current (and generates
the maximum drop across the load resistor). At the same time,
IOUT sinks no current (and generates no voltage drop). At
midscale, the outputs sink equal amounts of current, generating
equal voltage drops.
PLL CIRCUITRY
The AD9956 includes an RF divider (divide-by-R), a phase
frequency detector, and a programmable output current charge
pump. Incorporating these blocks together, users can generate
many useful circuits for frequency synthesis. A few simple
examples are shown in the Typical Application Circuits.
The RF divider accepts differential or single-ended signals up to
2.7 GHz. The RF divider also supplies the SYSCLK input to the
DDS. Because the DDS operates up to only 400 MSPS, device
function requires that for any RF input signal > 400 MHz, the
RF divider be engaged. The RF divider can be programmed to
take values of 1, 2, 4, or 8. The ratio for the divider is pro-
grammed in the control register. The output of the divider can
be routed to the input of the on-chip CML driver. For lower
frequency input signals, it is possible to use the divider to divide
the input signal to the CML driver and use the undivided input
of the divider as the SYSCLK input to the DDS, or vice versa. In
all cases, the clock to the DDS should not exceed 400 MSPS.
The on-chip phase frequency detector has two differential
inputs, PLLREF (the reference input) and PLLOSC (the feed-
back or oscillator input). These differential inputs can be driven
by single-ended signals; however, when doing so, tie the unused
input through a 100 pF capacitor to the analog supply (AVDD).
The maximum speed of the phase frequency detector inputs is
200 MHz. Each of the inputs has a buffer and a divider (÷M on
PLLREF and ÷N on PLLOSC) that operates at up to 655 MHz.
If the signal exceeds 200 MHz, however, the divider must be
used. The dividers are programmed through the control registers
and take any integer value between 1 and 16.
The PLLREF input also has the option of engaging an in-line
oscillator circuit. Engaging this circuit means that the PLLREF
input can be driven with a crystal in the of 20 MHz ≤ PLLREF ≤
30 MHz range.
The charge pump outputs a current in response to an error
signal generated in the phase frequency detector. The output
current is programmed through by placing a resistor (CP_RSET)
from the CP_RSET pin to ground. The value is dictated by the
following equation:
SET
CP_R
CP_OUT
1.55
=
This sets the charge pump’s reference output current. Also, a
programmable scaler multiplies this base value by any integer
from 1 to 8, programmable through the CP current scale bits in
the Control Function Register 2, CFR2<2:0>.
相关PDF资料 |
PDF描述 |
|---|---|
| S9S08DZ60F1MLH | MCU 60K FLASH MASK AUTO 64-LQFP |
| AD9952YSVZ | IC DDS 14BIT DAC 1.8V 48-TQFP |
| MC9S08DZ96MLF | MCU 8BIT 96K FLASH 48-LQFP |
| AD5933YRSZ | IC NTWK ANALYZER 12B 1MSP 16SSOP |
| MC908JL3EMPE | IC MCU 4K FLASH W/OSC 28-PDIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9956YCPZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL7 | 功能描述:IC SYNTHESIZER 1.8V 48LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9957 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| AD9957/PCBZ | 功能描述:BOARD EVAL AD9957 QUADRATURE MOD RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
发布紧急采购，3分钟左右您将得到回复。