参数资料
型号: AD9958BCPZ
厂商: Analog Devices Inc
文件页数: 12/44页
文件大小: 0K
描述: IC DDS DUAL 500MSPS DAC 56LFCSP
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
设计资源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
标准包装: 1
分辨率(位): 10 b
主 fclk: 500MHz
调节字宽(位): 32 b
电源电压: 1.71 V ~ 1.96 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-VFQFN 裸露焊盘,CSP
供应商设备封装: 56-LFCSP-VQ(8x8)
包装: 托盘
产品目录页面: 552 (CN2011-ZH PDF)
配用: AD9958/PCBZ-ND - BOARD EVALUATION FOR AD9958
AD9958
Data Sheet
Rev. B | Page 2 of 45
TABLE OF CONTENTS
REVISION HISTORY
4/13—Rev. A to Rev. B
Changes to Linear Sweep Mode Section and Setting the Slope of
the Linear Sweep............................................................................. 25
Changes to Figure 38 and Figure 39 Captions............................ 27
Changes to Ramp Rate Timer Section......................................... 28
Updated Outline Dimensions ....................................................... 44
7/08—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Inserted Figure 1; Renumbered Sequentially................................ 1
Changes to Input Level Parameter in Table 1 ............................... 4
Added Profile Pin Toggle Rate Parameter in Table 1................... 6
Changes to Layout ............................................................................ 8
Changes to Table 3............................................................................ 9
Added Equivalent Input and Output Circuits Section .............. 17
Changes to Reference Clock Input Circuitry Section................ 20
Change to Figure 35 ....................................................................... 21
Changes to Setting the Slope of the Linear Sweep Section ....... 25
Changes to Figure 37...................................................................... 26
Changes to Figure 38 and Figure 39 ............................................ 27
Changes to Figure 40...................................................................... 30
Added Table 25; Renumbered Sequentially ................................ 31
Changes to Figure 41...................................................................... 31
Changes to Figure 42, Serial Data I/O (SDIO_0, SDIO_1,
SDIO_3) Section, and Added Example Instruction Byte
Section.............................................................................................. 32
Added Table 27 ............................................................................... 33
Changes to Figure 46, Figure 47, Figure 48, and Figure 49 ...... 35
Changes to Register Maps and Bit Descriptions Section and
Added Endnote 2 to Table 28........................................................ 36
Added Endnote 1 to Table 30........................................................ 38
Added Exposed Pad Notation to Outline Dimensions ............. 44
9/05—Revision 0: Initial Version
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