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| 型号： | AD9959/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9959 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 设计资源： | Phase Coherent FSK Modulator (CN0186) AD9958/59 Eval Brd Schematics AD9958/59 Eval Brd Gerber Files AD9959 Eval Brd BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，直接数字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9959 |
| 主要属性： | 10 位数模转换器，32 位调节字宽 |
| 次要属性： | 4 通道 |
| 已供物品： | 板，线缆，软件 |
| 其它名称： | AD9959/PCB AD9959/PCB-ND Q2548077 |
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AD9959
Rev. B | Page 30 of 44
I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
RELATIONSHIPS
I/O_UPDATE and SYNC_CLK are used together to transfer
data from the serial I/O buffer to the active registers in the
device. Data in the buffer is inactive.
SYNC_CLK is a rising edge active signal. It is derived from
the system clock and a divide-by-4 frequency divider. The
SYNC_CLK, which is externally provided, can be used to
synchronize external hardware to the AD9959 internal clocks.
I/O_UPDATE initiates the start of a buffer transfer. It can be
sent synchronously or asynchronously relative to the SYNC_CLK.
If the setup time between these signals is met, then constant
latency (pipeline) to the DAC output exists. For example, if
repetitive changes to phase offset via the SPI port is desired, the
latency of those changes to the DAC output is constant; otherwise,
a time uncertainty of one SYNC_CLK period is present.
The I/O_UPDATE is essentially oversampled by the SYNC_CLK.
Therefore, I/O_UPDATE must have a minimum pulse width
greater than one SYNC_CLK period.
The timing diagram shown in Figure 40 depicts when data in
the buffer is transferred to the active registers.
SYNC_CLK
SYSCLK
AB
NN + 1
N – 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
N
N + 1
N + 2
I/O_UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. 05
24
6-
04
9
Figure 40. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD995PCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9960BSTZ | 功能描述:RFID应答器 MxFE for RFID Reader Transceiver RoHS:否 制造商:Murata 存储容量:512 bit 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AD9960BSTZRL | 功能描述:IC MXFE FOR RFID READER/TXRX RoHS:是 类别:RF/IF 和 RFID >> RFID IC 系列:AD9960B 其它有关文件:CR14 View All Specifications 标准包装:1 系列:- RF 型:收发器 频率:13.56MHz 特点:ISO14443-B 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SO 包装:Digi-Reel® 其它名称:497-5719-6 |
| AD9960XSTZ | 制造商:Analog Devices 功能描述:SINGLE-SUPPLY CABLE MODEM/SET-TOP BOX MIXED-SIGNAL FRONT END - Trays |
| AD9961 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-/12-Bit, Low Power, Broadband MxFE |
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