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参数资料
型号： AD9959/PCBZ
厂商： Analog Devices Inc
文件页数： 34/44页
文件大小： 0K
描述： BOARD EVALUATION FOR AD9959
产品培训模块： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
设计资源： Phase Coherent FSK Modulator (CN0186)
AD9958/59 Eval Brd Schematics
AD9958/59 Eval Brd Gerber Files
AD9959 Eval Brd BOM
标准包装： 1
主要目的： 计时，直接数字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9959
主要属性： 10 位数模转换器，32 位调节字宽
次要属性： 4 通道
已供物品： 板，线缆，软件
其它名称： AD9959/PCB
AD9959/PCB-ND
Q2548077
AD9959
Rev. B | Page 4 of 44
SPECIFICATIONS
AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; RSET = 1.91 kΩ; external reference clock frequency = 500 MSPS
(REFCLK multiplier bypassed), unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE CLOCK INPUT CHARACTERISTICS
See Figure 34 and Figure 35
Frequency Range
REFCLK Multiplier Bypassed
1
500
MHz
REFCLK Multiplier Enabled
10
125
MHz
Internal VCO Output Frequency Range
VCO Gain Control Bit Set High1
255
500
MHz
VCO Gain Control Bit Set Low1
100
160
MHz
Crystal REFCLK Source Range
20
30
MHz
Input Level
200
1000
mV
Measured at each pin (single-ended)
Input Voltage Bias Level
1.15
V
Input Capacitance
2
pF
Input Impedance
1500
Ω
Duty Cycle with REFCLK Multiplier Bypassed
45
55
%
Duty Cycle with REFCLK Multiplier Enabled
35
65
%
CLK Mode Select (Pin 24) Logic 1 Voltage
1.25
1.8
V
1.8 V digital input logic
CLK Mode Select (Pin 24) Logic 0 Voltage
0.5
V
1.8 V digital input logic
DAC OUTPUT CHARACTERISTICS
Must be referenced to AVDD
Resolution
10
Bits
Full-Scale Output Current
1.25
10
mA
Gain Error
10
+10
%FS
Channel-to-Channel Output Amplitude Matching Error
2.5
+2.5
%
Output Current Offset
1
25
μA
Differential Nonlinearity
±0.5
LSB
Integral Nonlinearity
±1.0
LSB
Output Capacitance
3
pF
Voltage Compliance Range
AVDD 0.50
AVDD + 0.50
V
Channel-to-Channel Isolation
65
dB
DAC supplies tied together
(see Figure 19)
WIDEBAND SFDR
The frequency range for wideband
SFDR is defined as dc to Nyquist
1 MHz to 20 MHz Analog Output
65
dBc
20 MHz to 60 MHz Analog Output
62
dBc
60 MHz to 100 MHz Analog Output
59
dBc
100 MHz to 150 MHz Analog Output
56
dBc
150 MHz to 200 MHz Analog Output
53
dBc
NARROW-BAND SFDR
1.1 MHz Analog Output (±10 kHz)
90
dBc
1.1 MHz Analog Output (±50 kHz)
88
dBc
1.1 MHz Analog Output (±250 kHz)
86
dBc
1.1 MHz Analog Output (±1 MHz)
85
dBc
15.1 MHz Analog Output (±10 kHz)
90
dBc
15.1 MHz Analog Output (±50 kHz)
87
dBc
15.1 MHz Analog Output (±250 kHz)
85
dBc
15.1 MHz Analog Output (±1 MHz)
83
dBc
40.1 MHz Analog Output (±10 kHz)
90
dBc
40.1 MHz Analog Output (±50 kHz)
87
dBc
40.1 MHz Analog Output (±250 kHz)
84
dBc
40.1 MHz Analog Output (±1 MHz)
82
dBc
75.1 MHz Analog Output (±10 kHz)
87
dBc
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