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参数资料
| 型号： | ADA4424-6ARUZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| 标准包装： | 2,500 |
| 滤波器类型： | SD/ED/HD |
| 滤波器数： | 6 |
| 滤波器阶数： | 5th |
| 电源电压： | 3.3V，5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
ADA4424-6
Rev. C | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
3.3 V Supply Voltage
3.6 V
5 V Supply Voltage
5.5 V
Digital Input Voltage (Pin 2 to Pin 5, Pin 8,
Pin 12, Pin 15, Pin 16, Pin 23)
3.6 V
Power Dissipation
See Figure 2
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +85°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to load drive
depends on the particular application. For each output, the
power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to the loads is equal to the sum of the
power dissipations due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA.
Figure 2 shows the maximum power dissipation in the package
vs. the ambient temperature for the 38-lead TSSOP (67.6°C/W)
on a JEDEC standard 4-layer board. θJA values are approximate.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
2.4
0
100
AMBIENT TEMPERATURE (°C)
M
AX
IM
UM
P
O
W
E
R
DI
S
IP
AT
IO
N
(
W
)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
10
20
30
40
50
60
70
80
90
08
55
0-
00
2
THERMAL RESISTANCE
θJA is specified for the device soldered to a high thermal
conductivity 4-layer (2s2p) circuit board, as described in
EIA/JESD 51-7.
Table 3.
Package Type
θJA
θJC
Unit
38-Lead TSSOP
67.6
14.0
°C/W
MAXIMUM POWER DISSIPATION
Figure 2. Maximum Power Dissipation vs.
Ambient Temperature for a 4-Layer Board
The maximum safe power dissipation in the ADA4424-6
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4424-6. Exceeding a
junction temperature of 150°C for an extended time can result
in changes in the silicon devices, potentially causing failure.
ESD CAUTION
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