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参数资料
| 型号： | ADA4424-6ARUZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| 标准包装： | 2,500 |
| 滤波器类型： | SD/ED/HD |
| 滤波器数： | 6 |
| 滤波器阶数： | 5th |
| 电源电压： | 3.3V，5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
ADA4424-6
Rev. C | Page 13 of 16
POWER-DOWN
The ADA4424-6 provides separate output enable pins for the
SD and ED/HD sections. In addition to powering down the Y,
C, and CVBS outputs, the SD_ENABLE pin, when driven low,
also places the S1/S2 output (S1/S2_OUT, Pin 34) in a high
impedance state. Likewise, driving the HD_ENABLE pin low
disables the component outputs (HY_OUT, HPb_OUT, and
HPr_OUT) and changes the L1, L2, and L3 outputs (Lx_OUT,
Pin 35 to Pin 37) to a high impedance state. Control details are
Table 12. Power-Down Control for SD Channels
SD_ENABLE
(Pin 8)
SD Outputs
(Y, C, CVBS)
S1/S2_OUT
(Pin 34)
Low (0)
Disabled
High-Z (Open)
High (1)
Enabled
Active
Table 13. Power-Down Control for ED/HD Channels
HD_ENABLE
(Pin 15)
ED/HD Outputs
(HY, HPb, HPr)
Lx_OUT (Pin 35,
Pin 36, Pin 37)
Low (0)
Disabled
High-Z (Open)
High (1)
Enabled
Active
CHARGE PUMP
The ADA4424-6 features an on-chip charge pump that supplies
a negative rail voltage for the output stages. To minimize internal
noise coupling, the charge pump uses an external connection to
the negative supply pins (VSS_SD and VSS_HD). These pins
should be connected to the C2/CP_OUT pin, each decoupled
with a 1.0 μF capacitor. It is also recommended to place a small
(1 Ω) series resistor in this connection. This forms a low-pass
filter with the VSS decoupling capacitors and further reduces
coupled noise. The charge pump also requires two 4.7 μF ceramic
capacitors, one connected across the C1a and C1b pins, and one
connected from the C2/CP_OUT pin to ground. The recom-
mended charge pump configuration is shown in the application
diagram (Figure 18).
With the black or zero level of the outputs placed at approx-
imately ground potential, the outputs can swing up to 1.6 V in
the negative direction. This eliminates the need for large output
coupling capacitors because the input-referred dc offsets does not
exceed ±100 mV (depending on the selected cancellation mode).
PRINTED CIRCUIT BOARD (PCB) LAYOUT
As with all high speed applications, attention to the PCB layout
is of paramount importance. When designing with the ADA4424-6,
adhere to standard high speed layout practices. A solid ground
plane is recommended, and surface-mount, ceramic power supply
decoupling capacitors should be placed as close as possible to the
supply pins. Connect all of the ADA4424-6 GND pins to the
ground plane with traces that are as short as possible. Controlled
impedance traces of the shortest length possible should be used
to connect to the signal I/O pins and should not pass over any
voids in the ground plane. A 75 Ω impedance level is typically
used in video applications. When driving transmission lines,
include series termination resistors on the signal outputs of the
ADA4424-6.
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