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| 型号： | ADA4841-2YR-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/21页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADA4841-2YR |
| 标准包装： | 1 |
| 每 IC 通道数： | 2 - 双 |
| 放大器类型： | 电压反馈 |
| 板类型： | 裸（未填充） |
| 已供物品： | 板 |
| 已用 IC / 零件： | 8-SOIC 封装 |
ADA4841-1/ADA4841-2
Rev. E | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
PD = Quiescent Power + (Total Drive Power Load Power)
Table 4.
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
See Figure 5
Common-Mode Input Voltage
VS 0.5 V to +VS + 0.5 V
Differential Input Voltage
±1.8 V
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +125°C
Lead Temperature
JEDEC J-STD-20
Junction Temperature
150°C
()
L
OUT
L
OUT
S
D
R
V
R
V
I
V
P
2
×
+
×
=
RMS output voltages should be considered. If RL is referenced
to VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
() (
)
L
S
D
R
V
I
V
P
2
4
/
+
×
=
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
In single-supply operation with RL referenced to VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θJA.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC_N
(125°C/W), the 6-lead SOT-23 (170°C/W), 8-lead MSOP
(145°C/W), and 8-lead LFCSP_WD (103°C/W) on a JEDEC
standard 4-layer board. θJA values are approximations.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for device soldered in circuit board for surface-mount
packages.
Table 5. Thermal Resistance
2.0
0
–55
125
05
61
4-
0
61
AMBIENT TEMPERATURE (°C)
MA
X
IMU
M
PO
W
E
R
D
ISS
IP
A
T
IO
N
(W
)
1.5
1.0
0.5
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115
SOT-23
SOIC
MSOP
LFCSP
Package Type
θJA
Unit
8-lead SOIC_N
125
°C/W
6-Lead SOT-23
170
°C/W
8-lead MSOP
130
°C/W
8-Lead LFCSP_WD
103
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4841-1/
ADA4841-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
amplifiers. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the amplifier’s drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
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